Lines Matching +full:zynqmp +full:- +full:qspi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU106
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
20 model = "ZynqMP ZCU106 RevA";
21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
33 spi0 = &qspi;
39 stdout-path = "serial0:115200n8";
47 gpio-keys {
48 compatible = "gpio-keys";
50 switch-19 {
54 wakeup-source;
60 compatible = "gpio-leds";
61 heartbeat-led {
64 linux,default-trigger = "heartbeat";
68 ina226-u76 {
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
72 ina226-u77 {
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
76 ina226-u78 {
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
80 ina226-u87 {
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
84 ina226-u85 {
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
88 ina226-u86 {
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
92 ina226-u93 {
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
96 ina226-u88 {
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
100 ina226-u15 {
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
104 ina226-u92 {
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
108 ina226-u79 {
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
112 ina226-u81 {
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
116 ina226-u80 {
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
120 ina226-u84 {
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
124 ina226-u16 {
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
128 ina226-u65 {
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
132 ina226-u74 {
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
136 ina226-u75 {
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <48000000>;
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <114285000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_can1_default>;
199 phy-handle = <&phy0>;
200 phy-mode = "rgmii-id";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_gem3_default>;
203 phy0: ethernet-phy@c {
205 ti,rx-internal-delay = <0x8>;
206 ti,tx-internal-delay = <0xa>;
207 ti,fifo-depth = <0x1>;
208 ti,dp83867-rxctrl-strap-quirk;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_gpio_default>;
220 clock-frequency = <400000>;
221 pinctrl-names = "default", "gpio";
222 pinctrl-0 = <&pinctrl_i2c0_default>;
223 pinctrl-1 = <&pinctrl_i2c0_gpio>;
224 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
225 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
230 gpio-controller; /* interrupt not connected */
231 #gpio-cells = <2>;
235 * 0 - SFP_SI5328_INT_ALM
236 * 1 - HDMI_SI5328_INT_ALM
237 * 5 - IIC_MUX_RESET_B
238 * 6 - GEM3_EXP_RESET_B
239 * 10 - FMC_HPC0_PRSNT_M2C_B
240 * 11 - FMC_HPC1_PRSNT_M2C_B
241 * 2-4, 7, 12-17 - not connected
248 gpio-controller;
249 #gpio-cells = <2>;
253 * 0 - VCCPSPLL_EN
254 * 1 - MGTRAVCC_EN
255 * 2 - MGTRAVTT_EN
256 * 3 - VCCPSDDRPLL_EN
257 * 4 - MIO26_PMU_INPUT_LS
258 * 5 - PL_PMBUS_ALERT
259 * 6 - PS_PMBUS_ALERT
260 * 7 - MAXIM_PMBUS_ALERT
261 * 10 - PL_DDR4_VTERM_EN
262 * 11 - PL_DDR4_VPP_2V5_EN
263 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
264 * 13 - PS_DIMM_SUSPEND_EN
265 * 14 - PS_DDR4_VTERM_EN
266 * 15 - PS_DDR4_VPP_2V5_EN
267 * 16 - 17 - not connected
271 i2c-mux@75 { /* u60 */
273 #address-cells = <1>;
274 #size-cells = <0>;
277 #address-cells = <1>;
278 #size-cells = <0>;
283 #io-channel-cells = <1>;
284 label = "ina226-u76";
286 shunt-resistor = <5000>;
290 #io-channel-cells = <1>;
291 label = "ina226-u77";
293 shunt-resistor = <5000>;
297 #io-channel-cells = <1>;
298 label = "ina226-u78";
300 shunt-resistor = <5000>;
304 #io-channel-cells = <1>;
305 label = "ina226-u87";
307 shunt-resistor = <5000>;
311 #io-channel-cells = <1>;
312 label = "ina226-u85";
314 shunt-resistor = <5000>;
318 #io-channel-cells = <1>;
319 label = "ina226-u86";
321 shunt-resistor = <5000>;
325 #io-channel-cells = <1>;
326 label = "ina226-u93";
328 shunt-resistor = <5000>;
332 #io-channel-cells = <1>;
333 label = "ina226-u88";
335 shunt-resistor = <5000>;
339 #io-channel-cells = <1>;
340 label = "ina226-u15";
342 shunt-resistor = <5000>;
346 #io-channel-cells = <1>;
347 label = "ina226-u92";
349 shunt-resistor = <5000>;
352 i2c@1 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 reg = <1>;
359 #io-channel-cells = <1>;
360 label = "ina226-u79";
362 shunt-resistor = <2000>;
366 #io-channel-cells = <1>;
367 label = "ina226-u81";
369 shunt-resistor = <5000>;
373 #io-channel-cells = <1>;
374 label = "ina226-u80";
376 shunt-resistor = <5000>;
380 #io-channel-cells = <1>;
381 label = "ina226-u84";
383 shunt-resistor = <5000>;
387 #io-channel-cells = <1>;
388 label = "ina226-u16";
390 shunt-resistor = <5000>;
394 #io-channel-cells = <1>;
395 label = "ina226-u65";
397 shunt-resistor = <5000>;
401 #io-channel-cells = <1>;
402 label = "ina226-u74";
404 shunt-resistor = <5000>;
408 #io-channel-cells = <1>;
409 label = "ina226-u75";
411 shunt-resistor = <5000>;
415 #address-cells = <1>;
416 #size-cells = <0>;
418 /* MAXIM_PMBUS - 00 */
455 max15303@1a { /* u49 */
459 max15303@1b { /* u8 */
463 max15303@1d { /* u18 */
483 clock-frequency = <400000>;
484 pinctrl-names = "default", "gpio";
485 pinctrl-0 = <&pinctrl_i2c1_default>;
486 pinctrl-1 = <&pinctrl_i2c1_gpio>;
487 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
488 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
490 /* PL i2c via PCA9306 - u45 */
491 i2c-mux@74 { /* u34 */
493 #address-cells = <1>;
494 #size-cells = <0>;
497 #address-cells = <1>;
498 #size-cells = <0>;
501 * IIC_EEPROM 1kB memory which uses 256B blocks
503 * 0 - 256B address 0x54
504 * 256B - 512B address 0x55
505 * 512B - 768B address 0x56
506 * 768B - 1024B address 0x57
513 i2c@1 {
514 #address-cells = <1>;
515 #size-cells = <0>;
516 reg = <1>;
517 si5341: clock-generator@36 { /* SI5341 - u69 */
520 #clock-cells = <2>;
521 #address-cells = <1>;
522 #size-cells = <0>;
524 clock-names = "xtal";
525 clock-output-names = "si5341";
528 /* refclk0 for PS-GT, used for DP */
530 always-on;
533 /* refclk2 for PS-GT, used for USB3 */
535 always-on;
538 /* refclk3 for PS-GT, used for SATA */
540 always-on;
545 always-on;
550 always-on;
555 always-on;
561 #address-cells = <1>;
562 #size-cells = <0>;
564 si570_1: clock-generator@5d { /* USER SI570 - u42 */
565 #clock-cells = <0>;
568 temperature-stability = <50>;
569 factory-fout = <300000000>;
570 clock-frequency = <300000000>;
571 clock-output-names = "si570_user";
575 #address-cells = <1>;
576 #size-cells = <0>;
578 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
579 #clock-cells = <0>;
582 temperature-stability = <50>; /* copy from zc702 */
583 factory-fout = <156250000>;
584 clock-frequency = <148500000>;
585 clock-output-names = "si570_mgt";
589 #address-cells = <1>;
590 #size-cells = <0>;
592 /* SI5328 - u20 */
595 #address-cells = <1>;
596 #size-cells = <0>;
598 temp@4c {/* lm96163 - u128 */
603 /* 6 - 7 unconnected */
606 i2c-mux@75 {
608 #address-cells = <1>;
609 #size-cells = <0>;
613 #address-cells = <1>;
614 #size-cells = <0>;
618 i2c@1 {
619 #address-cells = <1>;
620 #size-cells = <0>;
621 reg = <1>;
625 #address-cells = <1>;
626 #size-cells = <0>;
631 #address-cells = <1>;
632 #size-cells = <0>;
637 #address-cells = <1>;
638 #size-cells = <0>;
643 #address-cells = <1>;
644 #size-cells = <0>;
649 #address-cells = <1>;
650 #size-cells = <0>;
652 /* SEP 1 */
655 #address-cells = <1>;
656 #size-cells = <0>;
665 pinctrl_i2c0_default: i2c0-default {
673 bias-pull-up;
674 slew-rate = <SLEW_RATE_SLOW>;
675 power-source = <IO_STANDARD_LVCMOS18>;
679 pinctrl_i2c0_gpio: i2c0-gpio {
687 slew-rate = <SLEW_RATE_SLOW>;
688 power-source = <IO_STANDARD_LVCMOS18>;
692 pinctrl_i2c1_default: i2c1-default {
700 bias-pull-up;
701 slew-rate = <SLEW_RATE_SLOW>;
702 power-source = <IO_STANDARD_LVCMOS18>;
706 pinctrl_i2c1_gpio: i2c1-gpio {
714 slew-rate = <SLEW_RATE_SLOW>;
715 power-source = <IO_STANDARD_LVCMOS18>;
719 pinctrl_uart0_default: uart0-default {
727 slew-rate = <SLEW_RATE_SLOW>;
728 power-source = <IO_STANDARD_LVCMOS18>;
731 conf-rx {
733 bias-high-impedance;
736 conf-tx {
738 bias-disable;
742 pinctrl_uart1_default: uart1-default {
750 slew-rate = <SLEW_RATE_SLOW>;
751 power-source = <IO_STANDARD_LVCMOS18>;
754 conf-rx {
756 bias-high-impedance;
759 conf-tx {
761 bias-disable;
765 pinctrl_usb0_default: usb0-default {
773 slew-rate = <SLEW_RATE_SLOW>;
774 power-source = <IO_STANDARD_LVCMOS18>;
777 conf-rx {
779 bias-high-impedance;
782 conf-tx {
785 bias-disable;
789 pinctrl_gem3_default: gem3-default {
797 slew-rate = <SLEW_RATE_SLOW>;
798 power-source = <IO_STANDARD_LVCMOS18>;
801 conf-rx {
804 bias-high-impedance;
805 low-power-disable;
808 conf-tx {
811 bias-disable;
812 low-power-enable;
815 mux-mdio {
820 conf-mdio {
822 slew-rate = <SLEW_RATE_SLOW>;
823 power-source = <IO_STANDARD_LVCMOS18>;
824 bias-disable;
828 pinctrl_can1_default: can1-default {
836 slew-rate = <SLEW_RATE_SLOW>;
837 power-source = <IO_STANDARD_LVCMOS18>;
840 conf-rx {
842 bias-high-impedance;
845 conf-tx {
847 bias-disable;
851 pinctrl_sdhci1_default: sdhci1-default {
859 slew-rate = <SLEW_RATE_SLOW>;
860 power-source = <IO_STANDARD_LVCMOS18>;
861 bias-disable;
864 mux-cd {
869 conf-cd {
871 bias-high-impedance;
872 bias-pull-up;
873 slew-rate = <SLEW_RATE_SLOW>;
874 power-source = <IO_STANDARD_LVCMOS18>;
877 mux-wp {
882 conf-wp {
884 bias-high-impedance;
885 bias-pull-up;
886 slew-rate = <SLEW_RATE_SLOW>;
887 power-source = <IO_STANDARD_LVCMOS18>;
891 pinctrl_gpio_default: gpio-default {
899 slew-rate = <SLEW_RATE_SLOW>;
900 power-source = <IO_STANDARD_LVCMOS18>;
903 mux-msp {
908 conf-msp {
910 slew-rate = <SLEW_RATE_SLOW>;
911 power-source = <IO_STANDARD_LVCMOS18>;
914 conf-pull-up {
916 bias-pull-up;
919 conf-pull-none {
921 bias-disable;
930 clock-names = "ref1", "ref2", "ref3";
933 &qspi {
936 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
937 #address-cells = <1>;
938 #size-cells = <1>;
940 spi-tx-bus-width = <1>;
941 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
942 spi-max-frequency = <108000000>; /* Based on DC1 spec */
953 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
954 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
955 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
956 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
957 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
958 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
959 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
960 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
961 phy-names = "sata-phy";
962 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
971 no-1-8-v;
972 pinctrl-names = "default";
973 pinctrl-0 = <&pinctrl_sdhci1_default>;
974 xlnx,mio-bank = <1>;
979 pinctrl-names = "default";
980 pinctrl-0 = <&pinctrl_uart0_default>;
985 pinctrl-names = "default";
986 pinctrl-0 = <&pinctrl_uart1_default>;
992 pinctrl-names = "default";
993 pinctrl-0 = <&pinctrl_usb0_default>;
994 phy-names = "usb3-phy";
1002 maximum-speed = "super-speed";
1015 phy-names = "dp-phy0", "dp-phy1";
1016 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
1017 <&psgtr 0 PHY_TYPE_DP 1 3>;