Lines Matching +full:zynqmp +full:- +full:qspi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU104 RevC";
20 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
31 spi0 = &qspi;
37 stdout-path = "serial0:115200n8";
46 compatible = "iio-hwmon";
47 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <125000000>;
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <26000000>;
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <27000000>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_can1_default>;
113 phy-handle = <&phy0>;
114 phy-mode = "rgmii-id";
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_gem3_default>;
117 phy0: ethernet-phy@c {
119 ti,rx-internal-delay = <0x8>;
120 ti,tx-internal-delay = <0xa>;
121 ti,fifo-depth = <0x1>;
122 ti,dp83867-rxctrl-strap-quirk;
132 clock-frequency = <400000>;
133 pinctrl-names = "default", "gpio";
134 pinctrl-0 = <&pinctrl_i2c1_default>;
135 pinctrl-1 = <&pinctrl_i2c1_gpio>;
136 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
137 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
142 gpio-controller;
143 #gpio-cells = <2>;
147 * 0 - IRPS5401_ALERT_B
148 * 1 - HDMI_8T49N241_INT_ALM
149 * 2 - MAX6643_OT_B
150 * 3 - MAX6643_FANFAIL_B
151 * 5 - IIC_MUX_RESET_B
152 * 6 - GEM3_EXP_RESET_B
153 * 7 - FMC_LPC_PRSNT_M2C_B
154 * 4, 10 - 17 - not connected
158 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
159 i2c-mux@74 { /* u34 */
161 #address-cells = <1>;
162 #size-cells = <0>;
165 #address-cells = <1>;
166 #size-cells = <0>;
169 * IIC_EEPROM 1kB memory which uses 256B blocks
171 * 0 - 256B address 0x54
172 * 256B - 512B address 0x55
173 * 512B - 768B address 0x56
174 * 768B - 1024B address 0x57
179 #address-cells = <1>;
180 #size-cells = <1>;
184 i2c@1 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 reg = <1>;
188 /* 8T49N287 - u182 */
192 #address-cells = <1>;
193 #size-cells = <0>;
195 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
199 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
206 #address-cells = <1>;
207 #size-cells = <0>;
211 #io-channel-cells = <1>;
213 shunt-resistor = <5000>;
218 #address-cells = <1>;
219 #size-cells = <0>;
224 #address-cells = <1>;
225 #size-cells = <0>;
236 pinctrl_can1_default: can1-default {
244 slew-rate = <SLEW_RATE_SLOW>;
245 power-source = <IO_STANDARD_LVCMOS18>;
246 drive-strength = <12>;
249 conf-rx {
251 bias-high-impedance;
254 conf-tx {
256 bias-disable;
260 pinctrl_i2c1_default: i2c1-default {
268 bias-pull-up;
269 slew-rate = <SLEW_RATE_SLOW>;
270 power-source = <IO_STANDARD_LVCMOS18>;
271 drive-strength = <12>;
275 pinctrl_i2c1_gpio: i2c1-gpio {
283 slew-rate = <SLEW_RATE_SLOW>;
284 power-source = <IO_STANDARD_LVCMOS18>;
285 drive-strength = <12>;
289 pinctrl_gem3_default: gem3-default {
297 slew-rate = <SLEW_RATE_SLOW>;
298 power-source = <IO_STANDARD_LVCMOS18>;
299 drive-strength = <12>;
302 conf-rx {
305 bias-high-impedance;
306 low-power-disable;
309 conf-tx {
312 bias-disable;
313 low-power-enable;
316 mux-mdio {
321 conf-mdio {
323 slew-rate = <SLEW_RATE_SLOW>;
324 power-source = <IO_STANDARD_LVCMOS18>;
325 bias-disable;
329 pinctrl_sdhci1_default: sdhci1-default {
337 slew-rate = <SLEW_RATE_SLOW>;
338 power-source = <IO_STANDARD_LVCMOS18>;
339 bias-disable;
340 drive-strength = <12>;
343 mux-cd {
348 conf-cd {
350 bias-high-impedance;
351 bias-pull-up;
352 slew-rate = <SLEW_RATE_SLOW>;
353 power-source = <IO_STANDARD_LVCMOS18>;
357 pinctrl_uart0_default: uart0-default {
365 slew-rate = <SLEW_RATE_SLOW>;
366 power-source = <IO_STANDARD_LVCMOS18>;
367 drive-strength = <12>;
370 conf-rx {
372 bias-high-impedance;
375 conf-tx {
377 bias-disable;
381 pinctrl_uart1_default: uart1-default {
389 slew-rate = <SLEW_RATE_SLOW>;
390 power-source = <IO_STANDARD_LVCMOS18>;
391 drive-strength = <12>;
394 conf-rx {
396 bias-high-impedance;
399 conf-tx {
401 bias-disable;
405 pinctrl_usb0_default: usb0-default {
413 slew-rate = <SLEW_RATE_SLOW>;
414 power-source = <IO_STANDARD_LVCMOS18>;
415 drive-strength = <12>;
418 conf-rx {
420 bias-high-impedance;
423 conf-tx {
426 bias-disable;
435 clock-names = "ref1", "ref2", "ref3";
438 &qspi {
441 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
442 #address-cells = <1>;
443 #size-cells = <1>;
445 spi-tx-bus-width = <1>;
446 spi-rx-bus-width = <4>;
447 spi-max-frequency = <108000000>; /* Based on DC1 spec */
458 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
459 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
460 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
461 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
462 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
463 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
464 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
465 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
466 phy-names = "sata-phy";
467 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
473 no-1-8-v;
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_sdhci1_default>;
476 xlnx,mio-bank = <1>;
477 disable-wp;
482 pinctrl-names = "default";
483 pinctrl-0 = <&pinctrl_uart0_default>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_uart1_default>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_usb0_default>;
497 phy-names = "usb3-phy";
505 maximum-speed = "super-speed";
518 phy-names = "dp-phy0", "dp-phy1";
519 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
520 <&psgtr 0 PHY_TYPE_DP 1 3>;