Lines Matching +full:io +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
39 stdout-path = "serial0:115200n8";
47 gpio-keys {
48 compatible = "gpio-keys";
50 switch-19 {
54 wakeup-source;
60 compatible = "gpio-leds";
61 heartbeat-led {
64 linux,default-trigger = "heartbeat";
68 ina226-u76 {
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
72 ina226-u77 {
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
76 ina226-u78 {
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
80 ina226-u87 {
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
84 ina226-u85 {
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
88 ina226-u86 {
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
92 ina226-u93 {
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
96 ina226-u88 {
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
100 ina226-u15 {
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
104 ina226-u92 {
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
108 ina226-u79 {
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
112 ina226-u81 {
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
116 ina226-u80 {
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
120 ina226-u84 {
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
124 ina226-u16 {
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
128 ina226-u65 {
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
132 ina226-u74 {
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
136 ina226-u75 {
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <48000000>;
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <114285000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_can1_default>;
199 phy-handle = <&phy0>;
200 phy-mode = "rgmii-id";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_gem3_default>;
203 phy0: ethernet-phy@21 {
205 ti,rx-internal-delay = <0x8>;
206 ti,tx-internal-delay = <0xa>;
207 ti,fifo-depth = <0x1>;
208 ti,dp83867-rxctrl-strap-quirk;
209 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_gpio_default>;
221 clock-frequency = <400000>;
222 pinctrl-names = "default", "gpio";
223 pinctrl-0 = <&pinctrl_i2c0_default>;
224 pinctrl-1 = <&pinctrl_i2c0_gpio>;
225 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
226 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
231 gpio-controller; /* IRQ not connected */
232 #gpio-cells = <2>;
233 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
236 gtr-sel0-hog {
237 gpio-hog;
239 output-low; /* PCIE = 0, DP = 1 */
240 line-name = "sel0";
242 gtr-sel1-hog {
243 gpio-hog;
245 output-high; /* PCIE = 0, DP = 1 */
246 line-name = "sel1";
248 gtr-sel2-hog {
249 gpio-hog;
251 output-high; /* PCIE = 0, USB0 = 1 */
252 line-name = "sel2";
254 gtr-sel3-hog {
255 gpio-hog;
257 output-high; /* PCIE = 0, SATA = 1 */
258 line-name = "sel3";
265 gpio-controller; /* IRQ not connected */
266 #gpio-cells = <2>;
267 …gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_…
273 i2c-mux@75 { /* u60 */
275 #address-cells = <1>;
276 #size-cells = <0>;
279 #address-cells = <1>;
280 #size-cells = <0>;
285 #io-channel-cells = <1>;
286 label = "ina226-u76";
288 shunt-resistor = <5000>;
292 #io-channel-cells = <1>;
293 label = "ina226-u77";
295 shunt-resistor = <5000>;
299 #io-channel-cells = <1>;
300 label = "ina226-u78";
302 shunt-resistor = <5000>;
306 #io-channel-cells = <1>;
307 label = "ina226-u87";
309 shunt-resistor = <5000>;
313 #io-channel-cells = <1>;
314 label = "ina226-u85";
316 shunt-resistor = <5000>;
320 #io-channel-cells = <1>;
321 label = "ina226-u86";
323 shunt-resistor = <5000>;
327 #io-channel-cells = <1>;
328 label = "ina226-u93";
330 shunt-resistor = <5000>;
334 #io-channel-cells = <1>;
335 label = "ina226-u88";
337 shunt-resistor = <5000>;
341 #io-channel-cells = <1>;
342 label = "ina226-u15";
344 shunt-resistor = <5000>;
348 #io-channel-cells = <1>;
349 label = "ina226-u92";
351 shunt-resistor = <5000>;
355 #address-cells = <1>;
356 #size-cells = <0>;
361 #io-channel-cells = <1>;
362 label = "ina226-u79";
364 shunt-resistor = <2000>;
368 #io-channel-cells = <1>;
369 label = "ina226-u81";
371 shunt-resistor = <5000>;
375 #io-channel-cells = <1>;
376 label = "ina226-u80";
378 shunt-resistor = <5000>;
382 #io-channel-cells = <1>;
383 label = "ina226-u84";
385 shunt-resistor = <5000>;
389 #io-channel-cells = <1>;
390 label = "ina226-u16";
392 shunt-resistor = <5000>;
396 #io-channel-cells = <1>;
397 label = "ina226-u65";
399 shunt-resistor = <5000>;
403 #io-channel-cells = <1>;
404 label = "ina226-u74";
406 shunt-resistor = <5000>;
410 #io-channel-cells = <1>;
411 label = "ina226-u75";
413 shunt-resistor = <5000>;
417 #address-cells = <1>;
418 #size-cells = <0>;
420 /* MAXIM_PMBUS - 00 */
485 clock-frequency = <400000>;
486 pinctrl-names = "default", "gpio";
487 pinctrl-0 = <&pinctrl_i2c1_default>;
488 pinctrl-1 = <&pinctrl_i2c1_gpio>;
489 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
490 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
492 /* PL i2c via PCA9306 - u45 */
493 i2c-mux@74 { /* u34 */
495 #address-cells = <1>;
496 #size-cells = <0>;
499 #address-cells = <1>;
500 #size-cells = <0>;
505 * 0 - 256B address 0x54
506 * 256B - 512B address 0x55
507 * 512B - 768B address 0x56
508 * 768B - 1024B address 0x57
516 #address-cells = <1>;
517 #size-cells = <0>;
519 si5341: clock-generator@36 { /* SI5341 - u69 */
522 #clock-cells = <2>;
523 #address-cells = <1>;
524 #size-cells = <0>;
526 clock-names = "xtal";
527 clock-output-names = "si5341";
530 /* refclk0 for PS-GT, used for DP */
532 always-on;
535 /* refclk2 for PS-GT, used for USB3 */
537 always-on;
540 /* refclk3 for PS-GT, used for SATA */
542 always-on;
545 /* refclk4 for PS-GT, used for PCIE slot */
547 always-on;
550 /* refclk5 for PS-GT, used for PCIE */
552 always-on;
557 always-on;
562 always-on;
567 always-on;
572 #address-cells = <1>;
573 #size-cells = <0>;
575 si570_1: clock-generator@5d { /* USER SI570 - u42 */
576 #clock-cells = <0>;
579 temperature-stability = <50>;
580 factory-fout = <300000000>;
581 clock-frequency = <300000000>;
582 clock-output-names = "si570_user";
586 #address-cells = <1>;
587 #size-cells = <0>;
589 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
590 #clock-cells = <0>;
593 temperature-stability = <50>; /* copy from zc702 */
594 factory-fout = <156250000>;
595 clock-frequency = <148500000>;
596 clock-output-names = "si570_mgt";
600 #address-cells = <1>;
601 #size-cells = <0>;
603 /* SI5328 - u20 */
605 /* 5 - 7 unconnected */
608 i2c-mux@75 {
610 #address-cells = <1>;
611 #size-cells = <0>;
615 #address-cells = <1>;
616 #size-cells = <0>;
621 #address-cells = <1>;
622 #size-cells = <0>;
627 #address-cells = <1>;
628 #size-cells = <0>;
633 #address-cells = <1>;
634 #size-cells = <0>;
639 #address-cells = <1>;
640 #size-cells = <0>;
645 #address-cells = <1>;
646 #size-cells = <0>;
651 #address-cells = <1>;
652 #size-cells = <0>;
657 #address-cells = <1>;
658 #size-cells = <0>;
667 pinctrl_i2c0_default: i2c0-default {
675 bias-pull-up;
676 slew-rate = <SLEW_RATE_SLOW>;
677 power-source = <IO_STANDARD_LVCMOS18>;
681 pinctrl_i2c0_gpio: i2c0-gpio {
689 slew-rate = <SLEW_RATE_SLOW>;
690 power-source = <IO_STANDARD_LVCMOS18>;
694 pinctrl_i2c1_default: i2c1-default {
702 bias-pull-up;
703 slew-rate = <SLEW_RATE_SLOW>;
704 power-source = <IO_STANDARD_LVCMOS18>;
708 pinctrl_i2c1_gpio: i2c1-gpio {
716 slew-rate = <SLEW_RATE_SLOW>;
717 power-source = <IO_STANDARD_LVCMOS18>;
721 pinctrl_uart0_default: uart0-default {
729 slew-rate = <SLEW_RATE_SLOW>;
730 power-source = <IO_STANDARD_LVCMOS18>;
733 conf-rx {
735 bias-high-impedance;
738 conf-tx {
740 bias-disable;
744 pinctrl_uart1_default: uart1-default {
752 slew-rate = <SLEW_RATE_SLOW>;
753 power-source = <IO_STANDARD_LVCMOS18>;
756 conf-rx {
758 bias-high-impedance;
761 conf-tx {
763 bias-disable;
767 pinctrl_usb0_default: usb0-default {
775 slew-rate = <SLEW_RATE_SLOW>;
776 power-source = <IO_STANDARD_LVCMOS18>;
779 conf-rx {
781 bias-high-impedance;
784 conf-tx {
787 bias-disable;
791 pinctrl_gem3_default: gem3-default {
799 slew-rate = <SLEW_RATE_SLOW>;
800 power-source = <IO_STANDARD_LVCMOS18>;
803 conf-rx {
806 bias-high-impedance;
807 low-power-disable;
810 conf-tx {
813 bias-disable;
814 low-power-enable;
817 mux-mdio {
822 conf-mdio {
824 slew-rate = <SLEW_RATE_SLOW>;
825 power-source = <IO_STANDARD_LVCMOS18>;
826 bias-disable;
830 pinctrl_can1_default: can1-default {
838 slew-rate = <SLEW_RATE_SLOW>;
839 power-source = <IO_STANDARD_LVCMOS18>;
842 conf-rx {
844 bias-high-impedance;
847 conf-tx {
849 bias-disable;
853 pinctrl_sdhci1_default: sdhci1-default {
861 slew-rate = <SLEW_RATE_SLOW>;
862 power-source = <IO_STANDARD_LVCMOS18>;
863 bias-disable;
866 mux-cd {
871 conf-cd {
873 bias-high-impedance;
874 bias-pull-up;
875 slew-rate = <SLEW_RATE_SLOW>;
876 power-source = <IO_STANDARD_LVCMOS18>;
879 mux-wp {
884 conf-wp {
886 bias-high-impedance;
887 bias-pull-up;
888 slew-rate = <SLEW_RATE_SLOW>;
889 power-source = <IO_STANDARD_LVCMOS18>;
893 pinctrl_gpio_default: gpio-default {
894 mux-sw {
899 conf-sw {
901 slew-rate = <SLEW_RATE_SLOW>;
902 power-source = <IO_STANDARD_LVCMOS18>;
905 mux-msp {
910 conf-msp {
912 slew-rate = <SLEW_RATE_SLOW>;
913 power-source = <IO_STANDARD_LVCMOS18>;
916 conf-pull-up {
918 bias-pull-up;
921 conf-pull-none {
923 bias-disable;
936 clock-names = "ref0", "ref1", "ref2", "ref3";
942 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
943 #address-cells = <1>;
944 #size-cells = <1>;
946 spi-tx-bus-width = <1>;
947 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
948 spi-max-frequency = <108000000>; /* Based on DC1 spec */
959 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
960 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
961 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
962 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
963 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
964 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
965 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
966 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
967 phy-names = "sata-phy";
978 no-1-8-v;
979 pinctrl-names = "default";
980 pinctrl-0 = <&pinctrl_sdhci1_default>;
981 xlnx,mio-bank = <1>;
986 pinctrl-names = "default";
987 pinctrl-0 = <&pinctrl_uart0_default>;
992 pinctrl-names = "default";
993 pinctrl-0 = <&pinctrl_uart1_default>;
999 pinctrl-names = "default";
1000 pinctrl-0 = <&pinctrl_usb0_default>;
1001 phy-names = "usb3-phy";
1009 maximum-speed = "super-speed";
1022 phy-names = "dp-phy0";