Lines Matching +full:0 +full:x03880000
19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x43000014 0x00 0x4>;
44 reg = <0x00 0x41c00000 0x00 0x100000>;
45 ranges = <0x00 0x00 0x41c00000 0x100000>;
52 /* Proxy 0 addressing */
53 reg = <0x00 0x4301c000 0x00 0x178>;
56 pinctrl-single,function-mask = <0xffffffff>;
61 reg = <0x00 0x42200000 0x00 0x400>;
73 reg = <0x0 0x40f00000 0x0 0x20000>;
76 ranges = <0x0 0x0 0x40f00000 0x20000>;
80 reg = <0x4040 0x4>;
88 reg = <0x00 0x42300000 0x00 0x200>;
98 reg = <0x00 0x40a00000 0x00 0x200>;
108 reg = <0x00 0x42110000 0x00 0x100>;
116 ti,davinci-gpio-unbanked = <0>;
118 clocks = <&k3_clks 115 0>;
124 reg = <0x00 0x42100000 0x00 0x100>;
132 ti,davinci-gpio-unbanked = <0>;
134 clocks = <&k3_clks 116 0>;
140 reg = <0x00 0x42120000 0x00 0x100>;
143 #size-cells = <0>;
151 reg = <0x00 0x40b00000 0x00 0x100>;
154 #size-cells = <0>;
162 reg = <0x00 0x40b10000 0x00 0x100>;
165 #size-cells = <0>;
173 reg = <0x00 0x40528000 0x00 0x200>,
174 <0x00 0x40500000 0x00 0x8000>;
177 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
182 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
187 reg = <0x00 0x40568000 0x00 0x200>,
188 <0x00 0x40540000 0x00 0x8000>;
191 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
196 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
203 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
211 reg = <0x0 0x2b800000 0x0 0x400000>,
212 <0x0 0x2b000000 0x0 0x400000>,
213 <0x0 0x28590000 0x0 0x100>,
214 <0x0 0x2a500000 0x0 0x40000>;
217 ti,sci-rm-range-gp-rings = <0x1>;
225 reg = <0x0 0x285c0000 0x0 0x100>,
226 <0x0 0x2a800000 0x0 0x40000>,
227 <0x0 0x2aa00000 0x0 0x40000>;
235 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
236 <0x0f>; /* TX_HCHAN */
237 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
238 <0x0b>; /* RX_HCHAN */
239 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
247 reg = <0x0 0x46000000 0x0 0x200000>;
249 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
255 dmas = <&mcu_udmap 0xf000>,
256 <&mcu_udmap 0xf001>,
257 <&mcu_udmap 0xf002>,
258 <&mcu_udmap 0xf003>,
259 <&mcu_udmap 0xf004>,
260 <&mcu_udmap 0xf005>,
261 <&mcu_udmap 0xf006>,
262 <&mcu_udmap 0xf007>,
263 <&mcu_udmap 0x7000>;
270 #size-cells = <0>;
276 ti,syscon-efuse = <&mcu_conf 0x200>;
283 reg = <0x0 0xf00 0x0 0x100>;
285 #size-cells = <0>;
293 reg = <0x0 0x3d000 0x0 0x400>;