Lines Matching +full:tchsh +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
16 compatible = "ti,j721e-sk", "ti,j721e";
20 stdout-path = "serial2:115200n8";
31 reserved_memory: reserved-memory {
32 #address-cells = <2>;
33 #size-cells = <2>;
39 no-map;
42 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
43 compatible = "shared-dma-pool";
45 no-map;
48 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
49 compatible = "shared-dma-pool";
51 no-map;
54 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
55 compatible = "shared-dma-pool";
57 no-map;
60 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
61 compatible = "shared-dma-pool";
63 no-map;
66 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
67 compatible = "shared-dma-pool";
69 no-map;
72 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
73 compatible = "shared-dma-pool";
75 no-map;
78 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
79 compatible = "shared-dma-pool";
81 no-map;
84 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
85 compatible = "shared-dma-pool";
87 no-map;
90 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
91 compatible = "shared-dma-pool";
93 no-map;
96 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
97 compatible = "shared-dma-pool";
99 no-map;
102 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
103 compatible = "shared-dma-pool";
105 no-map;
108 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
109 compatible = "shared-dma-pool";
111 no-map;
114 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
115 compatible = "shared-dma-pool";
117 no-map;
120 c66_0_memory_region: c66-memory@a6100000 {
121 compatible = "shared-dma-pool";
123 no-map;
126 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
127 compatible = "shared-dma-pool";
129 no-map;
132 c66_1_memory_region: c66-memory@a7100000 {
133 compatible = "shared-dma-pool";
135 no-map;
138 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
139 compatible = "shared-dma-pool";
141 no-map;
144 c71_0_memory_region: c71-memory@a8100000 {
145 compatible = "shared-dma-pool";
147 no-map;
150 rtos_ipc_memory_region: ipc-memories@aa000000 {
153 no-map;
157 vusb_main: fixedregulator-vusb-main5v0 {
159 compatible = "regulator-fixed";
160 regulator-name = "vusb-main5v0";
161 regulator-min-microvolt = <5000000>;
162 regulator-max-microvolt = <5000000>;
163 regulator-always-on;
164 regulator-boot-on;
167 vsys_3v3: fixedregulator-vsys3v3 {
169 compatible = "regulator-fixed";
170 regulator-name = "vsys_3v3";
171 regulator-min-microvolt = <3300000>;
172 regulator-max-microvolt = <3300000>;
173 vin-supply = <&vusb_main>;
174 regulator-always-on;
175 regulator-boot-on;
178 vdd_mmc1: fixedregulator-sd {
179 compatible = "regulator-fixed";
180 pinctrl-names = "default";
181 pinctrl-0 = <&vdd_mmc1_en_pins_default>;
182 regulator-name = "vdd_mmc1";
183 regulator-min-microvolt = <3300000>;
184 regulator-max-microvolt = <3300000>;
185 regulator-boot-on;
186 enable-active-high;
187 vin-supply = <&vsys_3v3>;
191 vdd_sd_dv_alt: gpio-regulator-tps659411 {
192 compatible = "regulator-gpio";
193 pinctrl-names = "default";
194 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
195 regulator-name = "tps659411";
196 regulator-min-microvolt = <1800000>;
197 regulator-max-microvolt = <3300000>;
198 regulator-boot-on;
199 vin-supply = <&vsys_3v3>;
205 dp_pwr_3v3: fixedregulator-dp-prw {
206 compatible = "regulator-fixed";
207 regulator-name = "dp-pwr";
208 regulator-min-microvolt = <3300000>;
209 regulator-max-microvolt = <3300000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&dp_pwr_en_pins_default>;
213 enable-active-high;
217 compatible = "dp-connector";
219 type = "full-size";
220 dp-pwr-supply = <&dp_pwr_3v3>;
224 remote-endpoint = <&dp0_out>;
229 hdmi-connector {
230 compatible = "hdmi-connector";
234 pinctrl-names = "default";
235 pinctrl-0 = <&hdmi_hpd_pins_default>;
237 ddc-i2c-bus = <&main_i2c1>;
240 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
244 remote-endpoint = <&tfp410_out>;
249 dvi-bridge {
252 pinctrl-names = "default";
253 pinctrl-0 = <&hdmi_pdn_pins_default>;
255 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
259 #address-cells = <1>;
260 #size-cells = <0>;
266 remote-endpoint = <&dpi1_out>;
267 pclk-sample = <1>;
275 remote-endpoint =
284 main_mmc1_pins_default: main-mmc1-pins-default {
285 pinctrl-single,pins = <
297 main_uart0_pins_default: main-uart0-pins-default {
298 pinctrl-single,pins = <
306 main_i2c0_pins_default: main-i2c0-pins-default {
307 pinctrl-single,pins = <
313 main_i2c1_pins_default: main-i2c1-pins-default {
314 pinctrl-single,pins = <
320 main_i2c3_pins_default: main-i2c3-pins-default {
321 pinctrl-single,pins = <
327 main_usbss0_pins_default: main-usbss0-pins-default {
328 pinctrl-single,pins = <
334 main_usbss1_pins_default: main-usbss1-pins-default {
335 pinctrl-single,pins = <
340 dp0_pins_default: dp0-pins-default {
341 pinctrl-single,pins = <
346 dp_pwr_en_pins_default: dp-pwr-en-pins-default {
347 pinctrl-single,pins = <
352 dss_vout0_pins_default: dss-vout0-pins-default {
353 pinctrl-single,pins = <
385 hdmi_hpd_pins_default: hdmi-hpd-pins-default {
386 pinctrl-single,pins = <
391 hdmi_pdn_pins_default: hdmi-pdn-pins-default {
392 pinctrl-single,pins = <
398 ekey_reset_pins_default: ekey-reset-pns-pins-default {
399 pinctrl-single,pins = <
406 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
407 pinctrl-single,pins = <
423 mcu_mdio_pins_default: mcu-mdio1-pins-default {
424 pinctrl-single,pins = <
430 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
431 pinctrl-single,pins = <
446 vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
447 pinctrl-single,pins = <
452 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
453 pinctrl-single,pins = <
458 wkup_i2c0_pins_default: wkup-i2c0-pins-default {
459 pinctrl-single,pins = <
466 mkey_reset_pins_default: mkey-reset-pns-pins-default {
467 pinctrl-single,pins = <
479 pinctrl-names = "default";
480 pinctrl-0 = <&main_uart0_pins_default>;
482 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
527 vmmc-supply = <&vdd_mmc1>;
528 vqmmc-supply = <&vdd_sd_dv_alt>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&main_mmc1_pins_default>;
531 ti,driver-strength-ohm = <50>;
532 disable-wp;
541 pinctrl-names = "default";
542 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
545 compatible = "jedec,spi-nor";
547 spi-tx-bus-width = <8>;
548 spi-rx-bus-width = <8>;
549 spi-max-frequency = <25000000>;
550 cdns,tshsl-ns = <60>;
551 cdns,tsd2d-ns = <60>;
552 cdns,tchsh-ns = <60>;
553 cdns,tslch-ns = <60>;
554 cdns,read-delay = <4>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&main_i2c0_pins_default>;
566 clock-frequency = <400000>;
568 i2c-mux@71 {
570 #address-cells = <1>;
571 #size-cells = <0>;
576 #address-cells = <1>;
577 #size-cells = <0>;
583 #address-cells = <1>;
584 #size-cells = <0>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&main_i2c1_pins_default>;
594 clock-frequency = <100000>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&main_i2c3_pins_default>;
605 clock-frequency = <400000>;
607 i2c-mux@70 {
609 #address-cells = <1>;
610 #size-cells = <0>;
615 #address-cells = <1>;
616 #size-cells = <0>;
622 #address-cells = <1>;
623 #size-cells = <0>;
673 firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
677 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
681 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
690 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
691 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
697 cdns,num-lanes = <2>;
698 #phy-cells = <0>;
699 cdns,phy-type = <PHY_TYPE_USB3>;
708 cdns,phy-type = <PHY_TYPE_DP>;
709 cdns,num-lanes = <4>;
710 cdns,max-bit-rate = <5400>;
711 #phy-cells = <0>;
717 phy-names = "dpphy";
718 pinctrl-names = "default";
719 pinctrl-0 = <&dp0_pins_default>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&main_usbss0_pins_default>;
725 ti,vbus-divider;
730 maximum-speed = "super-speed";
732 phy-names = "cdns3,usb3-phy";
738 cdns,num-lanes = <1>;
739 #phy-cells = <0>;
740 cdns,phy-type = <PHY_TYPE_USB3>;
746 pinctrl-names = "default";
747 pinctrl-0 = <&main_usbss1_pins_default>;
748 ti,vbus-divider;
753 maximum-speed = "super-speed";
755 phy-names = "cdns3,usb3-phy";
769 pinctrl-names = "default";
770 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
774 phy0: ethernet-phy@0 {
776 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
777 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
782 phy-mode = "rgmii-rxid";
783 phy-handle = <&phy0>;
787 pinctrl-names = "default";
788 pinctrl-0 = <&dss_vout0_pins_default>;
790 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
794 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
801 #address-cells = <1>;
802 #size-cells = <0>;
808 remote-endpoint = <&dp0_in>;
816 remote-endpoint = <&tfp410_in>;
822 #address-cells = <1>;
823 #size-cells = <0>;
828 remote-endpoint = <&dpi0_out>;
835 remote-endpoint = <&dp_connector_in>;
903 cdns,num-lanes = <1>;
904 #phy-cells = <0>;
905 cdns,phy-type = <PHY_TYPE_PCIE>;
913 cdns,num-lanes = <2>;
914 #phy-cells = <0>;
915 cdns,phy-type = <PHY_TYPE_PCIE>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&ekey_reset_pins_default>;
923 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
926 phy-names = "pcie-phy";
927 num-lanes = <1>;
931 pinctrl-names = "default";
932 pinctrl-0 = <&mkey_reset_pins_default>;
933 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
936 phy-names = "pcie-phy";
937 num-lanes = <2>;
948 phy-names = "pcie-phy";
949 num-lanes = <1>;
955 phy-names = "pcie-phy";
956 num-lanes = <2>;
989 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
990 ti,mbox-rx = <0 0 0>;
991 ti,mbox-tx = <1 0 0>;
994 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
995 ti,mbox-rx = <2 0 0>;
996 ti,mbox-tx = <3 0 0>;
1003 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
1004 ti,mbox-rx = <0 0 0>;
1005 ti,mbox-tx = <1 0 0>;
1008 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
1009 ti,mbox-rx = <2 0 0>;
1010 ti,mbox-tx = <3 0 0>;
1017 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
1018 ti,mbox-rx = <0 0 0>;
1019 ti,mbox-tx = <1 0 0>;
1022 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
1023 ti,mbox-rx = <2 0 0>;
1024 ti,mbox-tx = <3 0 0>;
1031 mbox_c66_0: mbox-c66-0 {
1032 ti,mbox-rx = <0 0 0>;
1033 ti,mbox-tx = <1 0 0>;
1036 mbox_c66_1: mbox-c66-1 {
1037 ti,mbox-rx = <2 0 0>;
1038 ti,mbox-tx = <3 0 0>;
1045 mbox_c71_0: mbox-c71-0 {
1046 ti,mbox-rx = <0 0 0>;
1047 ti,mbox-tx = <1 0 0>;
1081 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
1087 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
1093 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1099 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1105 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1111 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1117 memory-region = <&c66_0_dma_memory_region>,
1123 memory-region = <&c66_1_dma_memory_region>,
1129 memory-region = <&c71_0_dma_memory_region>,