Lines Matching +full:0 +full:xf00000
21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
28 <0x00000008 0x80000000 0x00000000 0x80000000>;
37 reg = <0x00 0x9e800000 0x00 0x01800000>;
38 alignment = <0x1000>;
44 reg = <0x00 0xa0000000 0x00 0x100000>;
50 reg = <0x00 0xa0100000 0x00 0xf00000>;
56 reg = <0x00 0xa1000000 0x00 0x100000>;
62 reg = <0x00 0xa1100000 0x00 0xf00000>;
68 reg = <0x00 0xa2000000 0x00 0x100000>;
74 reg = <0x00 0xa2100000 0x00 0xf00000>;
80 reg = <0x00 0xa3000000 0x00 0x100000>;
86 reg = <0x00 0xa3100000 0x00 0xf00000>;
92 reg = <0x00 0xa4000000 0x00 0x100000>;
98 reg = <0x00 0xa4100000 0x00 0xf00000>;
104 reg = <0x00 0xa5000000 0x00 0x100000>;
110 reg = <0x00 0xa5100000 0x00 0xf00000>;
116 reg = <0x00 0xa6000000 0x00 0x100000>;
122 reg = <0x00 0xa6100000 0x00 0xf00000>;
128 reg = <0x00 0xa7000000 0x00 0x100000>;
134 reg = <0x00 0xa7100000 0x00 0xf00000>;
140 reg = <0x00 0xa8000000 0x00 0x100000>;
146 reg = <0x00 0xa8100000 0x00 0xf00000>;
151 reg = <0x00 0xaa000000 0x00 0x01c00000>;
152 alignment = <0x1000>;
181 pinctrl-0 = <&vdd_mmc1_en_pins_default>;
194 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
201 states = <1800000 0x0>,
202 <3300000 0x1>;
211 pinctrl-0 = <&dp_pwr_en_pins_default>;
212 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */
235 pinctrl-0 = <&hdmi_hpd_pins_default>;
240 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
253 pinctrl-0 = <&hdmi_pdn_pins_default>;
256 ti,deskew = <0>;
260 #size-cells = <0>;
262 port@0 {
263 reg = <0>;
286 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
287 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
288 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
289 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
290 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
291 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
292 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
293 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
299 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
300 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
301 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
302 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
308 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
309 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
315 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
316 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
322 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
323 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
329 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
330 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
336 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
342 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
348 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
354 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
355 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
356 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
357 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
358 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
359 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
360 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
361 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
362 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
363 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
364 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
365 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
366 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
367 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
368 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
369 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
370 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
371 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
372 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
373 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
374 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
375 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
376 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
377 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
378 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
379 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
380 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
381 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
387 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
393 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
400 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
408 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
409 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
410 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
411 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
412 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
413 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
414 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
415 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
416 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
417 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
418 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
419 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
425 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
426 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
432 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
433 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
434 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
435 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
436 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
437 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
438 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
439 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
440 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
441 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
442 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
448 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
454 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
460 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
461 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
468 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
480 pinctrl-0 = <&main_uart0_pins_default>;
530 pinctrl-0 = <&main_mmc1_pins_default>;
542 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
544 flash@0 {
546 reg = <0x0>;
565 pinctrl-0 = <&main_i2c0_pins_default>;
571 #size-cells = <0>;
572 reg = <0x71>;
575 i2c@0 {
577 #size-cells = <0>;
578 reg = <0>;
584 #size-cells = <0>;
592 pinctrl-0 = <&main_i2c1_pins_default>;
604 pinctrl-0 = <&main_i2c3_pins_default>;
610 #size-cells = <0>;
611 reg = <0x70>;
614 i2c@0 {
616 #size-cells = <0>;
617 reg = <0>;
623 #size-cells = <0>;
695 serdes3_usb_link: phy@0 {
696 reg = <0>;
698 #phy-cells = <0>;
705 torrent_phy_dp: phy@0 {
706 reg = <0>;
711 #phy-cells = <0>;
719 pinctrl-0 = <&dp0_pins_default>;
724 pinctrl-0 = <&main_usbss0_pins_default>;
739 #phy-cells = <0>;
747 pinctrl-0 = <&main_usbss1_pins_default>;
770 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
774 phy0: ethernet-phy@0 {
775 reg = <0>;
788 pinctrl-0 = <&dss_vout0_pins_default>;
802 #size-cells = <0>;
804 port@0 {
805 reg = <0>;
823 #size-cells = <0>;
825 port@0 {
826 reg = <0>;
901 serdes0_pcie_link: phy@0 {
902 reg = <0>;
904 #phy-cells = <0>;
911 serdes1_pcie_link: phy@0 {
912 reg = <0>;
914 #phy-cells = <0>;
922 pinctrl-0 = <&ekey_reset_pins_default>;
932 pinctrl-0 = <&mkey_reset_pins_default>;
990 ti,mbox-rx = <0 0 0>;
991 ti,mbox-tx = <1 0 0>;
995 ti,mbox-rx = <2 0 0>;
996 ti,mbox-tx = <3 0 0>;
1004 ti,mbox-rx = <0 0 0>;
1005 ti,mbox-tx = <1 0 0>;
1009 ti,mbox-rx = <2 0 0>;
1010 ti,mbox-tx = <3 0 0>;
1018 ti,mbox-rx = <0 0 0>;
1019 ti,mbox-tx = <1 0 0>;
1023 ti,mbox-rx = <2 0 0>;
1024 ti,mbox-tx = <3 0 0>;
1031 mbox_c66_0: mbox-c66-0 {
1032 ti,mbox-rx = <0 0 0>;
1033 ti,mbox-tx = <1 0 0>;
1037 ti,mbox-rx = <2 0 0>;
1038 ti,mbox-tx = <3 0 0>;
1045 mbox_c71_0: mbox-c71-0 {
1046 ti,mbox-rx = <0 0 0>;
1047 ti,mbox-tx = <1 0 0>;