Lines Matching +full:0 +full:x41010000
19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x0 0x43000014 0x0 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
67 reg = <0x00 0x41c00000 0x00 0x100000>;
68 ranges = <0x0 0x00 0x41c00000 0x100000>;
75 reg = <0x00 0x42300000 0x00 0x100>;
80 clocks = <&k3_clks 287 0>;
86 reg = <0x00 0x40a00000 0x00 0x100>;
91 clocks = <&k3_clks 149 0>;
97 reg = <0x00 0x42200000 0x00 0x400>;
109 reg = <0x0 0x42110000 0x0 0x100>;
117 ti,davinci-gpio-unbanked = <0>;
119 clocks = <&k3_clks 113 0>;
125 reg = <0x0 0x42100000 0x0 0x100>;
133 ti,davinci-gpio-unbanked = <0>;
135 clocks = <&k3_clks 114 0>;
141 reg = <0x0 0x40b00000 0x0 0x100>;
144 #size-cells = <0>;
146 clocks = <&k3_clks 194 0>;
152 reg = <0x0 0x40b10000 0x0 0x100>;
155 #size-cells = <0>;
157 clocks = <&k3_clks 195 0>;
163 reg = <0x0 0x42120000 0x0 0x100>;
166 #size-cells = <0>;
168 clocks = <&k3_clks 197 0>;
174 reg = <0x0 0x47000000 0x0 0x100>;
181 reg = <0x0 0x47040000 0x0 0x100>,
182 <0x5 0x00000000 0x1 0x0000000>;
186 cdns,trigger-address = <0x0>;
187 clocks = <&k3_clks 103 0>;
188 assigned-clocks = <&k3_clks 103 0>;
193 #size-cells = <0>;
198 reg = <0x0 0x47050000 0x0 0x100>,
199 <0x7 0x00000000 0x1 0x00000000>;
203 cdns,trigger-address = <0x0>;
204 clocks = <&k3_clks 104 0>;
207 #size-cells = <0>;
213 reg = <0x0 0x40200000 0x0 0x1000>;
215 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
216 clocks = <&k3_clks 0 1>;
217 assigned-clocks = <&k3_clks 0 3>;
220 dmas = <&main_udmap 0x7400>,
221 <&main_udmap 0x7401>;
232 reg = <0x0 0x40210000 0x0 0x1000>;
239 dmas = <&main_udmap 0x7402>,
240 <&main_udmap 0x7403>;
253 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
261 reg = <0x0 0x2b800000 0x0 0x400000>,
262 <0x0 0x2b000000 0x0 0x400000>,
263 <0x0 0x28590000 0x0 0x100>,
264 <0x0 0x2a500000 0x0 0x40000>;
267 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
275 reg = <0x0 0x285c0000 0x0 0x100>,
276 <0x0 0x2a800000 0x0 0x40000>,
277 <0x0 0x2aa00000 0x0 0x40000>;
286 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
287 <0x0f>; /* TX_HCHAN */
288 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
289 <0x0b>; /* RX_HCHAN */
290 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
298 reg = <0x0 0x46000000 0x0 0x200000>;
300 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
306 dmas = <&mcu_udmap 0xf000>,
307 <&mcu_udmap 0xf001>,
308 <&mcu_udmap 0xf002>,
309 <&mcu_udmap 0xf003>,
310 <&mcu_udmap 0xf004>,
311 <&mcu_udmap 0xf005>,
312 <&mcu_udmap 0xf006>,
313 <&mcu_udmap 0xf007>,
314 <&mcu_udmap 0x7000>;
321 #size-cells = <0>;
327 ti,syscon-efuse = <&mcu_conf 0x200>;
334 reg = <0x0 0xf00 0x0 0x100>;
336 #size-cells = <0>;
344 reg = <0x0 0x3d000 0x0 0x400>;
359 ranges = <0x41000000 0x00 0x41000000 0x20000>,
360 <0x41400000 0x00 0x41400000 0x20000>;
365 reg = <0x41000000 0x00008000>,
366 <0x41010000 0x00008000>;
370 ti,sci-proc-ids = <0x01 0xff>;
380 reg = <0x41400000 0x00008000>,
381 <0x41410000 0x00008000>;
385 ti,sci-proc-ids = <0x02 0xff>;
396 reg = <0x00 0x40528000 0x00 0x200>,
397 <0x00 0x40500000 0x00 0x8000>;
400 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
405 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
410 reg = <0x00 0x40568000 0x00 0x200>,
411 <0x00 0x40540000 0x00 0x8000>;
414 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
419 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;