Lines Matching +full:cmn +full:- +full:refclk1
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
10 #include <dt-bindings/mux/ti-serdes.h>
13 cmn_refclk: clock-cmnrefclk {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <0>;
19 cmn_refclk1: clock-cmnrefclk1 {
20 #clock-cells = <0>;
21 compatible = "fixed-clock";
22 clock-frequency = <0>;
28 compatible = "mmio-sram";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 atf-sram@0 {
39 scm_conf: scm-conf@100000 {
40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 #address-cells = <1>;
43 #size-cells = <1>;
46 serdes_ln_ctrl: mux-controller@4080 {
47 compatible = "mmio-mux";
49 #mux-control-cells = <1>;
50 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
56 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
64 usb_serdes_mux: mux-controller@4000 {
65 compatible = "mmio-mux";
66 #mux-control-cells = <1>;
67 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
72 gic500: interrupt-controller@1800000 {
73 compatible = "arm,gic-v3";
74 #address-cells = <2>;
75 #size-cells = <2>;
77 #interrupt-cells = <3>;
78 interrupt-controller;
88 gic_its: msi-controller@1820000 {
89 compatible = "arm,gic-v3-its";
91 socionext,synquacer-pre-its = <0x1000000 0x400000>;
92 msi-controller;
93 #msi-cells = <1>;
97 main_gpio_intr: interrupt-controller@a00000 {
98 compatible = "ti,sci-intr";
100 ti,intr-trigger-type = <1>;
101 interrupt-controller;
102 interrupt-parent = <&gic500>;
103 #interrupt-cells = <1>;
105 ti,sci-dev-id = <131>;
106 ti,interrupt-ranges = <8 392 56>;
110 compatible = "simple-mfd";
111 #address-cells = <2>;
112 #size-cells = <2>;
114 dma-coherent;
115 dma-ranges;
117 ti,sci-dev-id = <199>;
119 main_navss_intr: interrupt-controller@310e0000 {
120 compatible = "ti,sci-intr";
122 ti,intr-trigger-type = <4>;
123 interrupt-controller;
124 interrupt-parent = <&gic500>;
125 #interrupt-cells = <1>;
127 ti,sci-dev-id = <213>;
128 ti,interrupt-ranges = <0 64 64>,
133 main_udmass_inta: interrupt-controller@33d00000 {
134 compatible = "ti,sci-inta";
136 interrupt-controller;
137 interrupt-parent = <&main_navss_intr>;
138 msi-controller;
139 #interrupt-cells = <0>;
141 ti,sci-dev-id = <209>;
142 ti,interrupt-ranges = <0 0 256>;
146 compatible = "ti,am654-secure-proxy";
147 #mbox-cells = <1>;
148 reg-names = "target_data", "rt", "scfg";
152 interrupt-names = "rx_011";
157 compatible = "arm,smmu-v3";
159 interrupt-parent = <&gic500>;
162 interrupt-names = "eventq", "gerror";
163 #iommu-cells = <1>;
167 compatible = "ti,am654-hwspinlock";
169 #hwlock-cells = <1>;
173 compatible = "ti,am654-mailbox";
175 #mbox-cells = <1>;
176 ti,mbox-num-users = <4>;
177 ti,mbox-num-fifos = <16>;
178 interrupt-parent = <&main_navss_intr>;
182 compatible = "ti,am654-mailbox";
184 #mbox-cells = <1>;
185 ti,mbox-num-users = <4>;
186 ti,mbox-num-fifos = <16>;
187 interrupt-parent = <&main_navss_intr>;
191 compatible = "ti,am654-mailbox";
193 #mbox-cells = <1>;
194 ti,mbox-num-users = <4>;
195 ti,mbox-num-fifos = <16>;
196 interrupt-parent = <&main_navss_intr>;
200 compatible = "ti,am654-mailbox";
202 #mbox-cells = <1>;
203 ti,mbox-num-users = <4>;
204 ti,mbox-num-fifos = <16>;
205 interrupt-parent = <&main_navss_intr>;
209 compatible = "ti,am654-mailbox";
211 #mbox-cells = <1>;
212 ti,mbox-num-users = <4>;
213 ti,mbox-num-fifos = <16>;
214 interrupt-parent = <&main_navss_intr>;
218 compatible = "ti,am654-mailbox";
220 #mbox-cells = <1>;
221 ti,mbox-num-users = <4>;
222 ti,mbox-num-fifos = <16>;
223 interrupt-parent = <&main_navss_intr>;
227 compatible = "ti,am654-mailbox";
229 #mbox-cells = <1>;
230 ti,mbox-num-users = <4>;
231 ti,mbox-num-fifos = <16>;
232 interrupt-parent = <&main_navss_intr>;
236 compatible = "ti,am654-mailbox";
238 #mbox-cells = <1>;
239 ti,mbox-num-users = <4>;
240 ti,mbox-num-fifos = <16>;
241 interrupt-parent = <&main_navss_intr>;
245 compatible = "ti,am654-mailbox";
247 #mbox-cells = <1>;
248 ti,mbox-num-users = <4>;
249 ti,mbox-num-fifos = <16>;
250 interrupt-parent = <&main_navss_intr>;
254 compatible = "ti,am654-mailbox";
256 #mbox-cells = <1>;
257 ti,mbox-num-users = <4>;
258 ti,mbox-num-fifos = <16>;
259 interrupt-parent = <&main_navss_intr>;
263 compatible = "ti,am654-mailbox";
265 #mbox-cells = <1>;
266 ti,mbox-num-users = <4>;
267 ti,mbox-num-fifos = <16>;
268 interrupt-parent = <&main_navss_intr>;
272 compatible = "ti,am654-mailbox";
274 #mbox-cells = <1>;
275 ti,mbox-num-users = <4>;
276 ti,mbox-num-fifos = <16>;
277 interrupt-parent = <&main_navss_intr>;
281 compatible = "ti,am654-navss-ringacc";
286 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
287 ti,num-rings = <1024>;
288 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
290 ti,sci-dev-id = <211>;
291 msi-parent = <&main_udmass_inta>;
294 main_udmap: dma-controller@31150000 {
295 compatible = "ti,j721e-navss-main-udmap";
299 reg-names = "gcfg", "rchanrt", "tchanrt";
300 msi-parent = <&main_udmass_inta>;
301 #dma-cells = <1>;
304 ti,sci-dev-id = <212>;
307 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
310 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
313 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
317 compatible = "ti,j721e-cpts";
319 reg-names = "cpts";
321 clock-names = "cpts";
322 interrupts-extended = <&main_navss_intr 391>;
323 interrupt-names = "cpts";
324 ti,cpts-periodic-outputs = <6>;
325 ti,cpts-ext-ts-inputs = <8>;
330 compatible = "ti,j721e-sa2ul";
332 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
333 #address-cells = <2>;
334 #size-cells = <2>;
339 dma-names = "tx", "rx1", "rx2";
340 dma-coherent;
343 compatible = "inside-secure,safexcel-eip76";
351 compatible = "pinctrl-single";
354 #pinctrl-cells = <1>;
355 pinctrl-single,register-width = <32>;
356 pinctrl-single,function-mask = <0xffffffff>;
360 compatible = "ti,j721e-wiz-16g";
361 #address-cells = <1>;
362 #size-cells = <1>;
363 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
365 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
366 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
367 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
368 num-lanes = <2>;
369 #reset-cells = <1>;
372 wiz0_pll0_refclk: pll0-refclk {
374 #clock-cells = <0>;
375 assigned-clocks = <&wiz0_pll0_refclk>;
376 assigned-clock-parents = <&k3_clks 292 11>;
379 wiz0_pll1_refclk: pll1-refclk {
381 #clock-cells = <0>;
382 assigned-clocks = <&wiz0_pll1_refclk>;
383 assigned-clock-parents = <&k3_clks 292 0>;
386 wiz0_refclk_dig: refclk-dig {
388 #clock-cells = <0>;
389 assigned-clocks = <&wiz0_refclk_dig>;
390 assigned-clock-parents = <&k3_clks 292 11>;
393 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
395 #clock-cells = <0>;
398 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
400 #clock-cells = <0>;
404 compatible = "ti,sierra-phy-t0";
405 reg-names = "serdes";
407 #address-cells = <1>;
408 #size-cells = <0>;
409 #clock-cells = <1>;
411 reset-names = "sierra_reset";
414 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
420 compatible = "ti,j721e-wiz-16g";
421 #address-cells = <1>;
422 #size-cells = <1>;
423 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
425 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
426 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
427 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
428 num-lanes = <2>;
429 #reset-cells = <1>;
432 wiz1_pll0_refclk: pll0-refclk {
434 #clock-cells = <0>;
435 assigned-clocks = <&wiz1_pll0_refclk>;
436 assigned-clock-parents = <&k3_clks 293 13>;
439 wiz1_pll1_refclk: pll1-refclk {
441 #clock-cells = <0>;
442 assigned-clocks = <&wiz1_pll1_refclk>;
443 assigned-clock-parents = <&k3_clks 293 0>;
446 wiz1_refclk_dig: refclk-dig {
448 #clock-cells = <0>;
449 assigned-clocks = <&wiz1_refclk_dig>;
450 assigned-clock-parents = <&k3_clks 293 13>;
453 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
455 #clock-cells = <0>;
458 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
460 #clock-cells = <0>;
464 compatible = "ti,sierra-phy-t0";
465 reg-names = "serdes";
467 #address-cells = <1>;
468 #size-cells = <0>;
469 #clock-cells = <1>;
471 reset-names = "sierra_reset";
474 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
480 compatible = "ti,j721e-wiz-16g";
481 #address-cells = <1>;
482 #size-cells = <1>;
483 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
485 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
486 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
487 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
488 num-lanes = <2>;
489 #reset-cells = <1>;
492 wiz2_pll0_refclk: pll0-refclk {
494 #clock-cells = <0>;
495 assigned-clocks = <&wiz2_pll0_refclk>;
496 assigned-clock-parents = <&k3_clks 294 11>;
499 wiz2_pll1_refclk: pll1-refclk {
501 #clock-cells = <0>;
502 assigned-clocks = <&wiz2_pll1_refclk>;
503 assigned-clock-parents = <&k3_clks 294 0>;
506 wiz2_refclk_dig: refclk-dig {
508 #clock-cells = <0>;
509 assigned-clocks = <&wiz2_refclk_dig>;
510 assigned-clock-parents = <&k3_clks 294 11>;
513 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
515 #clock-cells = <0>;
518 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
520 #clock-cells = <0>;
524 compatible = "ti,sierra-phy-t0";
525 reg-names = "serdes";
527 #address-cells = <1>;
528 #size-cells = <0>;
529 #clock-cells = <1>;
531 reset-names = "sierra_reset";
534 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
540 compatible = "ti,j721e-wiz-16g";
541 #address-cells = <1>;
542 #size-cells = <1>;
543 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
545 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
546 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
547 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
548 num-lanes = <2>;
549 #reset-cells = <1>;
552 wiz3_pll0_refclk: pll0-refclk {
554 #clock-cells = <0>;
555 assigned-clocks = <&wiz3_pll0_refclk>;
556 assigned-clock-parents = <&k3_clks 295 9>;
559 wiz3_pll1_refclk: pll1-refclk {
561 #clock-cells = <0>;
562 assigned-clocks = <&wiz3_pll1_refclk>;
563 assigned-clock-parents = <&k3_clks 295 0>;
566 wiz3_refclk_dig: refclk-dig {
568 #clock-cells = <0>;
569 assigned-clocks = <&wiz3_refclk_dig>;
570 assigned-clock-parents = <&k3_clks 295 9>;
573 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
575 #clock-cells = <0>;
578 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
580 #clock-cells = <0>;
584 compatible = "ti,sierra-phy-t0";
585 reg-names = "serdes";
587 #address-cells = <1>;
588 #size-cells = <0>;
589 #clock-cells = <1>;
591 reset-names = "sierra_reset";
594 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
600 compatible = "ti,j721e-pcie-host";
605 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
606 interrupt-names = "link_state";
609 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
610 max-link-speed = <3>;
611 num-lanes = <2>;
612 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
614 clock-names = "fck";
615 #address-cells = <3>;
616 #size-cells = <2>;
617 bus-range = <0x0 0xff>;
618 vendor-id = <0x104c>;
619 device-id = <0xb00d>;
620 msi-map = <0x0 &gic_its 0x0 0x10000>;
621 dma-coherent;
624 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
627 pcie0_ep: pcie-ep@2900000 {
628 compatible = "ti,j721e-pcie-ep";
633 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
634 interrupt-names = "link_state";
636 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
637 max-link-speed = <3>;
638 num-lanes = <2>;
639 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
641 clock-names = "fck";
642 max-functions = /bits/ 8 <6>;
643 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
644 dma-coherent;
648 compatible = "ti,j721e-pcie-host";
653 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
654 interrupt-names = "link_state";
657 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
658 max-link-speed = <3>;
659 num-lanes = <2>;
660 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
662 clock-names = "fck";
663 #address-cells = <3>;
664 #size-cells = <2>;
665 bus-range = <0x0 0xff>;
666 vendor-id = <0x104c>;
667 device-id = <0xb00d>;
668 msi-map = <0x0 &gic_its 0x10000 0x10000>;
669 dma-coherent;
672 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
675 pcie1_ep: pcie-ep@2910000 {
676 compatible = "ti,j721e-pcie-ep";
681 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
682 interrupt-names = "link_state";
684 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
685 max-link-speed = <3>;
686 num-lanes = <2>;
687 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
689 clock-names = "fck";
690 max-functions = /bits/ 8 <6>;
691 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
692 dma-coherent;
696 compatible = "ti,j721e-pcie-host";
701 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
702 interrupt-names = "link_state";
705 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
706 max-link-speed = <3>;
707 num-lanes = <2>;
708 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
710 clock-names = "fck";
711 #address-cells = <3>;
712 #size-cells = <2>;
713 bus-range = <0x0 0xff>;
714 vendor-id = <0x104c>;
715 device-id = <0xb00d>;
716 msi-map = <0x0 &gic_its 0x20000 0x10000>;
717 dma-coherent;
720 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
723 pcie2_ep: pcie-ep@2920000 {
724 compatible = "ti,j721e-pcie-ep";
729 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
730 interrupt-names = "link_state";
732 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
733 max-link-speed = <3>;
734 num-lanes = <2>;
735 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
737 clock-names = "fck";
738 max-functions = /bits/ 8 <6>;
739 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
740 dma-coherent;
744 compatible = "ti,j721e-pcie-host";
749 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
750 interrupt-names = "link_state";
753 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
754 max-link-speed = <3>;
755 num-lanes = <2>;
756 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
758 clock-names = "fck";
759 #address-cells = <3>;
760 #size-cells = <2>;
761 bus-range = <0x0 0xff>;
762 vendor-id = <0x104c>;
763 device-id = <0xb00d>;
764 msi-map = <0x0 &gic_its 0x30000 0x10000>;
765 dma-coherent;
768 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
771 pcie3_ep: pcie-ep@2930000 {
772 compatible = "ti,j721e-pcie-ep";
777 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
778 interrupt-names = "link_state";
780 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
781 max-link-speed = <3>;
782 num-lanes = <2>;
783 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
785 clock-names = "fck";
786 max-functions = /bits/ 8 <6>;
787 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
788 dma-coherent;
789 #address-cells = <2>;
790 #size-cells = <2>;
794 compatible = "ti,am64-wiz-10g";
795 #address-cells = <1>;
796 #size-cells = <1>;
797 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
799 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
800 assigned-clocks = <&k3_clks 297 9>;
801 assigned-clock-parents = <&k3_clks 297 10>;
802 assigned-clock-rates = <19200000>;
803 num-lanes = <4>;
804 #reset-cells = <1>;
805 #clock-cells = <1>;
814 compatible = "ti,j721e-serdes-10g";
817 reg-names = "torrent_phy", "dptx_phy";
820 reset-names = "torrent_reset";
822 clock-names = "refclk";
823 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
826 assigned-clock-parents = <&k3_clks 297 9>,
829 #address-cells = <1>;
830 #size-cells = <0>;
835 compatible = "ti,j721e-uart", "ti,am654-uart";
838 clock-frequency = <48000000>;
839 current-speed = <115200>;
840 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
842 clock-names = "fclk";
846 compatible = "ti,j721e-uart", "ti,am654-uart";
849 clock-frequency = <48000000>;
850 current-speed = <115200>;
851 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
853 clock-names = "fclk";
857 compatible = "ti,j721e-uart", "ti,am654-uart";
860 clock-frequency = <48000000>;
861 current-speed = <115200>;
862 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
864 clock-names = "fclk";
868 compatible = "ti,j721e-uart", "ti,am654-uart";
871 clock-frequency = <48000000>;
872 current-speed = <115200>;
873 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
875 clock-names = "fclk";
879 compatible = "ti,j721e-uart", "ti,am654-uart";
882 clock-frequency = <48000000>;
883 current-speed = <115200>;
884 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
886 clock-names = "fclk";
890 compatible = "ti,j721e-uart", "ti,am654-uart";
893 clock-frequency = <48000000>;
894 current-speed = <115200>;
895 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
897 clock-names = "fclk";
901 compatible = "ti,j721e-uart", "ti,am654-uart";
904 clock-frequency = <48000000>;
905 current-speed = <115200>;
906 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
908 clock-names = "fclk";
912 compatible = "ti,j721e-uart", "ti,am654-uart";
915 clock-frequency = <48000000>;
916 current-speed = <115200>;
917 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
919 clock-names = "fclk";
923 compatible = "ti,j721e-uart", "ti,am654-uart";
926 clock-frequency = <48000000>;
927 current-speed = <115200>;
928 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
930 clock-names = "fclk";
934 compatible = "ti,j721e-uart", "ti,am654-uart";
937 clock-frequency = <48000000>;
938 current-speed = <115200>;
939 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
941 clock-names = "fclk";
945 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
947 gpio-controller;
948 #gpio-cells = <2>;
949 interrupt-parent = <&main_gpio_intr>;
952 interrupt-controller;
953 #interrupt-cells = <2>;
955 ti,davinci-gpio-unbanked = <0>;
956 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
958 clock-names = "gpio";
962 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
964 gpio-controller;
965 #gpio-cells = <2>;
966 interrupt-parent = <&main_gpio_intr>;
968 interrupt-controller;
969 #interrupt-cells = <2>;
971 ti,davinci-gpio-unbanked = <0>;
972 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
974 clock-names = "gpio";
978 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
980 gpio-controller;
981 #gpio-cells = <2>;
982 interrupt-parent = <&main_gpio_intr>;
985 interrupt-controller;
986 #interrupt-cells = <2>;
988 ti,davinci-gpio-unbanked = <0>;
989 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
991 clock-names = "gpio";
995 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
997 gpio-controller;
998 #gpio-cells = <2>;
999 interrupt-parent = <&main_gpio_intr>;
1001 interrupt-controller;
1002 #interrupt-cells = <2>;
1004 ti,davinci-gpio-unbanked = <0>;
1005 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1007 clock-names = "gpio";
1011 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1013 gpio-controller;
1014 #gpio-cells = <2>;
1015 interrupt-parent = <&main_gpio_intr>;
1018 interrupt-controller;
1019 #interrupt-cells = <2>;
1021 ti,davinci-gpio-unbanked = <0>;
1022 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1024 clock-names = "gpio";
1028 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1030 gpio-controller;
1031 #gpio-cells = <2>;
1032 interrupt-parent = <&main_gpio_intr>;
1034 interrupt-controller;
1035 #interrupt-cells = <2>;
1037 ti,davinci-gpio-unbanked = <0>;
1038 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1040 clock-names = "gpio";
1044 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1046 gpio-controller;
1047 #gpio-cells = <2>;
1048 interrupt-parent = <&main_gpio_intr>;
1051 interrupt-controller;
1052 #interrupt-cells = <2>;
1054 ti,davinci-gpio-unbanked = <0>;
1055 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1057 clock-names = "gpio";
1061 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1063 gpio-controller;
1064 #gpio-cells = <2>;
1065 interrupt-parent = <&main_gpio_intr>;
1067 interrupt-controller;
1068 #interrupt-cells = <2>;
1070 ti,davinci-gpio-unbanked = <0>;
1071 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1073 clock-names = "gpio";
1077 compatible = "ti,j721e-sdhci-8bit";
1080 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1081 clock-names = "clk_ahb", "clk_xin";
1083 assigned-clocks = <&k3_clks 91 1>;
1084 assigned-clock-parents = <&k3_clks 91 2>;
1085 bus-width = <8>;
1086 mmc-hs200-1_8v;
1087 mmc-ddr-1_8v;
1088 ti,otap-del-sel-legacy = <0xf>;
1089 ti,otap-del-sel-mmc-hs = <0xf>;
1090 ti,otap-del-sel-ddr52 = <0x5>;
1091 ti,otap-del-sel-hs200 = <0x6>;
1092 ti,otap-del-sel-hs400 = <0x0>;
1093 ti,itap-del-sel-legacy = <0x10>;
1094 ti,itap-del-sel-mmc-hs = <0xa>;
1095 ti,itap-del-sel-ddr52 = <0x3>;
1096 ti,trm-icp = <0x8>;
1097 ti,strobe-sel = <0x77>;
1098 dma-coherent;
1102 compatible = "ti,j721e-sdhci-4bit";
1105 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1106 clock-names = "clk_ahb", "clk_xin";
1108 assigned-clocks = <&k3_clks 92 0>;
1109 assigned-clock-parents = <&k3_clks 92 1>;
1110 ti,otap-del-sel-legacy = <0x0>;
1111 ti,otap-del-sel-sd-hs = <0xf>;
1112 ti,otap-del-sel-sdr12 = <0xf>;
1113 ti,otap-del-sel-sdr25 = <0xf>;
1114 ti,otap-del-sel-sdr50 = <0xc>;
1115 ti,otap-del-sel-ddr50 = <0xc>;
1116 ti,itap-del-sel-legacy = <0x0>;
1117 ti,itap-del-sel-sd-hs = <0x0>;
1118 ti,itap-del-sel-sdr12 = <0x0>;
1119 ti,itap-del-sel-sdr25 = <0x0>;
1120 ti,itap-del-sel-ddr50 = <0x2>;
1121 ti,trm-icp = <0x8>;
1122 ti,clkbuf-sel = <0x7>;
1123 dma-coherent;
1124 sdhci-caps-mask = <0x2 0x0>;
1128 compatible = "ti,j721e-sdhci-4bit";
1131 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1132 clock-names = "clk_ahb", "clk_xin";
1134 assigned-clocks = <&k3_clks 93 0>;
1135 assigned-clock-parents = <&k3_clks 93 1>;
1136 ti,otap-del-sel-legacy = <0x0>;
1137 ti,otap-del-sel-sd-hs = <0xf>;
1138 ti,otap-del-sel-sdr12 = <0xf>;
1139 ti,otap-del-sel-sdr25 = <0xf>;
1140 ti,otap-del-sel-sdr50 = <0xc>;
1141 ti,otap-del-sel-ddr50 = <0xc>;
1142 ti,itap-del-sel-legacy = <0x0>;
1143 ti,itap-del-sel-sd-hs = <0x0>;
1144 ti,itap-del-sel-sdr12 = <0x0>;
1145 ti,itap-del-sel-sdr25 = <0x0>;
1146 ti,itap-del-sel-ddr50 = <0x2>;
1147 ti,trm-icp = <0x8>;
1148 ti,clkbuf-sel = <0x7>;
1149 dma-coherent;
1150 sdhci-caps-mask = <0x2 0x0>;
1153 usbss0: cdns-usb@4104000 {
1154 compatible = "ti,j721e-usb";
1156 dma-coherent;
1157 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1159 clock-names = "ref", "lpm";
1160 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1161 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1162 #address-cells = <2>;
1163 #size-cells = <2>;
1171 reg-names = "otg", "xhci", "dev";
1175 interrupt-names = "host",
1178 maximum-speed = "super-speed";
1183 usbss1: cdns-usb@4114000 {
1184 compatible = "ti,j721e-usb";
1186 dma-coherent;
1187 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1189 clock-names = "ref", "lpm";
1190 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1191 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1192 #address-cells = <2>;
1193 #size-cells = <2>;
1201 reg-names = "otg", "xhci", "dev";
1205 interrupt-names = "host",
1208 maximum-speed = "super-speed";
1214 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1219 clock-names = "fck";
1221 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1225 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1228 #address-cells = <1>;
1229 #size-cells = <0>;
1230 clock-names = "fck";
1232 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1236 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1241 clock-names = "fck";
1243 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1247 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1252 clock-names = "fck";
1254 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1258 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1263 clock-names = "fck";
1265 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1269 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1274 clock-names = "fck";
1276 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1280 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285 clock-names = "fck";
1287 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1290 ufs_wrapper: ufs-wrapper@4e80000 {
1291 compatible = "ti,j721e-ufs";
1293 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1295 assigned-clocks = <&k3_clks 277 1>;
1296 assigned-clock-parents = <&k3_clks 277 4>;
1298 #address-cells = <2>;
1299 #size-cells = <2>;
1302 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1305 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1307 clock-names = "core_clk", "phy_clk", "ref_clk";
1308 dma-coherent;
1312 mhdp: dp-bridge@a000000 {
1313 compatible = "ti,j721e-mhdp8546";
1320 reg-names = "mhdptx", "j721e-intg";
1324 interrupt-parent = <&gic500>;
1327 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1344 compatible = "ti,j721e-dss";
1367 reg-names = "common_m", "common_s0",
1379 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1381 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1387 interrupt-names = "common_m",
1397 compatible = "ti,am33xx-mcasp-audio";
1400 reg-names = "mpu","dat";
1403 interrupt-names = "tx", "rx";
1406 dma-names = "tx", "rx";
1409 clock-names = "fck";
1410 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1414 compatible = "ti,am33xx-mcasp-audio";
1417 reg-names = "mpu","dat";
1420 interrupt-names = "tx", "rx";
1423 dma-names = "tx", "rx";
1426 clock-names = "fck";
1427 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1431 compatible = "ti,am33xx-mcasp-audio";
1434 reg-names = "mpu","dat";
1437 interrupt-names = "tx", "rx";
1440 dma-names = "tx", "rx";
1443 clock-names = "fck";
1444 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1448 compatible = "ti,am33xx-mcasp-audio";
1451 reg-names = "mpu","dat";
1454 interrupt-names = "tx", "rx";
1457 dma-names = "tx", "rx";
1460 clock-names = "fck";
1461 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1465 compatible = "ti,am33xx-mcasp-audio";
1468 reg-names = "mpu","dat";
1471 interrupt-names = "tx", "rx";
1474 dma-names = "tx", "rx";
1477 clock-names = "fck";
1478 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1482 compatible = "ti,am33xx-mcasp-audio";
1485 reg-names = "mpu","dat";
1488 interrupt-names = "tx", "rx";
1491 dma-names = "tx", "rx";
1494 clock-names = "fck";
1495 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1499 compatible = "ti,am33xx-mcasp-audio";
1502 reg-names = "mpu","dat";
1505 interrupt-names = "tx", "rx";
1508 dma-names = "tx", "rx";
1511 clock-names = "fck";
1512 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1516 compatible = "ti,am33xx-mcasp-audio";
1519 reg-names = "mpu","dat";
1522 interrupt-names = "tx", "rx";
1525 dma-names = "tx", "rx";
1528 clock-names = "fck";
1529 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1533 compatible = "ti,am33xx-mcasp-audio";
1536 reg-names = "mpu","dat";
1539 interrupt-names = "tx", "rx";
1542 dma-names = "tx", "rx";
1545 clock-names = "fck";
1546 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1550 compatible = "ti,am33xx-mcasp-audio";
1553 reg-names = "mpu","dat";
1556 interrupt-names = "tx", "rx";
1559 dma-names = "tx", "rx";
1562 clock-names = "fck";
1563 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1567 compatible = "ti,am33xx-mcasp-audio";
1570 reg-names = "mpu","dat";
1573 interrupt-names = "tx", "rx";
1576 dma-names = "tx", "rx";
1579 clock-names = "fck";
1580 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1584 compatible = "ti,am33xx-mcasp-audio";
1587 reg-names = "mpu","dat";
1590 interrupt-names = "tx", "rx";
1593 dma-names = "tx", "rx";
1596 clock-names = "fck";
1597 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1601 compatible = "ti,j7-rti-wdt";
1604 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1605 assigned-clocks = <&k3_clks 252 1>;
1606 assigned-clock-parents = <&k3_clks 252 5>;
1610 compatible = "ti,j7-rti-wdt";
1613 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1614 assigned-clocks = <&k3_clks 253 1>;
1615 assigned-clock-parents = <&k3_clks 253 5>;
1619 compatible = "ti,j721e-r5fss";
1620 ti,cluster-mode = <1>;
1621 #address-cells = <1>;
1622 #size-cells = <1>;
1625 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1628 compatible = "ti,j721e-r5f";
1631 reg-names = "atcm", "btcm";
1633 ti,sci-dev-id = <245>;
1634 ti,sci-proc-ids = <0x06 0xff>;
1636 firmware-name = "j7-main-r5f0_0-fw";
1637 ti,atcm-enable = <1>;
1638 ti,btcm-enable = <1>;
1643 compatible = "ti,j721e-r5f";
1646 reg-names = "atcm", "btcm";
1648 ti,sci-dev-id = <246>;
1649 ti,sci-proc-ids = <0x07 0xff>;
1651 firmware-name = "j7-main-r5f0_1-fw";
1652 ti,atcm-enable = <1>;
1653 ti,btcm-enable = <1>;
1659 compatible = "ti,j721e-r5fss";
1660 ti,cluster-mode = <1>;
1661 #address-cells = <1>;
1662 #size-cells = <1>;
1665 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
1668 compatible = "ti,j721e-r5f";
1671 reg-names = "atcm", "btcm";
1673 ti,sci-dev-id = <247>;
1674 ti,sci-proc-ids = <0x08 0xff>;
1676 firmware-name = "j7-main-r5f1_0-fw";
1677 ti,atcm-enable = <1>;
1678 ti,btcm-enable = <1>;
1683 compatible = "ti,j721e-r5f";
1686 reg-names = "atcm", "btcm";
1688 ti,sci-dev-id = <248>;
1689 ti,sci-proc-ids = <0x09 0xff>;
1691 firmware-name = "j7-main-r5f1_1-fw";
1692 ti,atcm-enable = <1>;
1693 ti,btcm-enable = <1>;
1699 compatible = "ti,j721e-c66-dsp";
1703 reg-names = "l2sram", "l1pram", "l1dram";
1705 ti,sci-dev-id = <142>;
1706 ti,sci-proc-ids = <0x03 0xff>;
1708 firmware-name = "j7-c66_0-fw";
1712 compatible = "ti,j721e-c66-dsp";
1716 reg-names = "l2sram", "l1pram", "l1dram";
1718 ti,sci-dev-id = <143>;
1719 ti,sci-proc-ids = <0x04 0xff>;
1721 firmware-name = "j7-c66_1-fw";
1725 compatible = "ti,j721e-c71-dsp";
1728 reg-names = "l2sram", "l1dram";
1730 ti,sci-dev-id = <15>;
1731 ti,sci-proc-ids = <0x30 0xff>;
1733 firmware-name = "j7-c71_0-fw";
1737 compatible = "ti,j721e-icssg";
1739 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
1740 #address-cells = <1>;
1741 #size-cells = <1>;
1748 reg-names = "dram0", "dram1",
1753 compatible = "ti,pruss-cfg", "syscon";
1755 #address-cells = <1>;
1756 #size-cells = <1>;
1760 #address-cells = <1>;
1761 #size-cells = <0>;
1763 icssg0_coreclk_mux: coreclk-mux@3c {
1765 #clock-cells = <0>;
1768 assigned-clocks = <&icssg0_coreclk_mux>;
1769 assigned-clock-parents = <&k3_clks 119 1>;
1772 icssg0_iepclk_mux: iepclk-mux@30 {
1774 #clock-cells = <0>;
1777 assigned-clocks = <&icssg0_iepclk_mux>;
1778 assigned-clock-parents = <&icssg0_coreclk_mux>;
1783 icssg0_mii_rt: mii-rt@32000 {
1784 compatible = "ti,pruss-mii", "syscon";
1788 icssg0_mii_g_rt: mii-g-rt@33000 {
1789 compatible = "ti,pruss-mii-g", "syscon";
1793 icssg0_intc: interrupt-controller@20000 {
1794 compatible = "ti,icssg-intc";
1796 interrupt-controller;
1797 #interrupt-cells = <3>;
1806 interrupt-names = "host_intr0", "host_intr1",
1813 compatible = "ti,j721e-pru";
1817 reg-names = "iram", "control", "debug";
1818 firmware-name = "j7-pru0_0-fw";
1822 compatible = "ti,j721e-rtu";
1826 reg-names = "iram", "control", "debug";
1827 firmware-name = "j7-rtu0_0-fw";
1831 compatible = "ti,j721e-tx-pru";
1835 reg-names = "iram", "control", "debug";
1836 firmware-name = "j7-txpru0_0-fw";
1840 compatible = "ti,j721e-pru";
1844 reg-names = "iram", "control", "debug";
1845 firmware-name = "j7-pru0_1-fw";
1849 compatible = "ti,j721e-rtu";
1853 reg-names = "iram", "control", "debug";
1854 firmware-name = "j7-rtu0_1-fw";
1858 compatible = "ti,j721e-tx-pru";
1862 reg-names = "iram", "control", "debug";
1863 firmware-name = "j7-txpru0_1-fw";
1870 clock-names = "fck";
1871 #address-cells = <1>;
1872 #size-cells = <0>;
1878 compatible = "ti,j721e-icssg";
1880 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1889 reg-names = "dram0", "dram1",
1894 compatible = "ti,pruss-cfg", "syscon";
1896 #address-cells = <1>;
1897 #size-cells = <1>;
1901 #address-cells = <1>;
1902 #size-cells = <0>;
1904 icssg1_coreclk_mux: coreclk-mux@3c {
1906 #clock-cells = <0>;
1909 assigned-clocks = <&icssg1_coreclk_mux>;
1910 assigned-clock-parents = <&k3_clks 120 4>;
1913 icssg1_iepclk_mux: iepclk-mux@30 {
1915 #clock-cells = <0>;
1918 assigned-clocks = <&icssg1_iepclk_mux>;
1919 assigned-clock-parents = <&icssg1_coreclk_mux>;
1924 icssg1_mii_rt: mii-rt@32000 {
1925 compatible = "ti,pruss-mii", "syscon";
1929 icssg1_mii_g_rt: mii-g-rt@33000 {
1930 compatible = "ti,pruss-mii-g", "syscon";
1934 icssg1_intc: interrupt-controller@20000 {
1935 compatible = "ti,icssg-intc";
1937 interrupt-controller;
1938 #interrupt-cells = <3>;
1947 interrupt-names = "host_intr0", "host_intr1",
1954 compatible = "ti,j721e-pru";
1958 reg-names = "iram", "control", "debug";
1959 firmware-name = "j7-pru1_0-fw";
1963 compatible = "ti,j721e-rtu";
1967 reg-names = "iram", "control", "debug";
1968 firmware-name = "j7-rtu1_0-fw";
1972 compatible = "ti,j721e-tx-pru";
1976 reg-names = "iram", "control", "debug";
1977 firmware-name = "j7-txpru1_0-fw";
1981 compatible = "ti,j721e-pru";
1985 reg-names = "iram", "control", "debug";
1986 firmware-name = "j7-pru1_1-fw";
1990 compatible = "ti,j721e-rtu";
1994 reg-names = "iram", "control", "debug";
1995 firmware-name = "j7-rtu1_1-fw";
1999 compatible = "ti,j721e-tx-pru";
2003 reg-names = "iram", "control", "debug";
2004 firmware-name = "j7-txpru1_1-fw";
2011 clock-names = "fck";
2012 #address-cells = <1>;
2013 #size-cells = <0>;
2022 reg-names = "m_can", "message_ram";
2023 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2025 clock-names = "hclk", "cclk";
2028 interrupt-names = "int0", "int1";
2029 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2036 reg-names = "m_can", "message_ram";
2037 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2039 clock-names = "hclk", "cclk";
2042 interrupt-names = "int0", "int1";
2043 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2050 reg-names = "m_can", "message_ram";
2051 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2053 clock-names = "hclk", "cclk";
2056 interrupt-names = "int0", "int1";
2057 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2064 reg-names = "m_can", "message_ram";
2065 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2067 clock-names = "hclk", "cclk";
2070 interrupt-names = "int0", "int1";
2071 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2078 reg-names = "m_can", "message_ram";
2079 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2081 clock-names = "hclk", "cclk";
2084 interrupt-names = "int0", "int1";
2085 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2092 reg-names = "m_can", "message_ram";
2093 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2095 clock-names = "hclk", "cclk";
2098 interrupt-names = "int0", "int1";
2099 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2106 reg-names = "m_can", "message_ram";
2107 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2109 clock-names = "hclk", "cclk";
2112 interrupt-names = "int0", "int1";
2113 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2120 reg-names = "m_can", "message_ram";
2121 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2123 clock-names = "hclk", "cclk";
2126 interrupt-names = "int0", "int1";
2127 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2134 reg-names = "m_can", "message_ram";
2135 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2137 clock-names = "hclk", "cclk";
2140 interrupt-names = "int0", "int1";
2141 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2148 reg-names = "m_can", "message_ram";
2149 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2151 clock-names = "hclk", "cclk";
2154 interrupt-names = "int0", "int1";
2155 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2162 reg-names = "m_can", "message_ram";
2163 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2165 clock-names = "hclk", "cclk";
2168 interrupt-names = "int0", "int1";
2169 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2176 reg-names = "m_can", "message_ram";
2177 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2179 clock-names = "hclk", "cclk";
2182 interrupt-names = "int0", "int1";
2183 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2190 reg-names = "m_can", "message_ram";
2191 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2193 clock-names = "hclk", "cclk";
2196 interrupt-names = "int0", "int1";
2197 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2204 reg-names = "m_can", "message_ram";
2205 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2207 clock-names = "hclk", "cclk";
2210 interrupt-names = "int0", "int1";
2211 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;