Lines Matching +full:0 +full:x7fef000
14 #clock-cells = <0>;
16 clock-frequency = <0>;
20 #clock-cells = <0>;
22 clock-frequency = <0>;
29 reg = <0x0 0x70000000 0x0 0x800000>;
32 ranges = <0x0 0x0 0x70000000 0x800000>;
34 atf-sram@0 {
35 reg = <0x0 0x20000>;
41 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
44 ranges = <0x0 0x0 0x00100000 0x1c000>;
48 reg = <0x00004080 0x50>;
50 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
51 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
52 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
53 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
54 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
67 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
68 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
79 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
80 <0x00 0x01900000 0x00 0x100000>, /* GICR */
81 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
82 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
83 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
90 reg = <0x00 0x01820000 0x00 0x10000>;
91 socionext,synquacer-pre-its = <0x1000000 0x400000>;
99 reg = <0x00 0x00a00000 0x00 0x800>;
113 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
121 reg = <0x0 0x310e0000 0x0 0x4000>;
128 ti,interrupt-ranges = <0 64 64>,
135 reg = <0x0 0x33d00000 0x0 0x100000>;
139 #interrupt-cells = <0>;
142 ti,interrupt-ranges = <0 0 256>;
149 reg = <0x00 0x32c00000 0x00 0x100000>,
150 <0x00 0x32400000 0x00 0x100000>,
151 <0x00 0x32800000 0x00 0x100000>;
158 reg = <0x0 0x36600000 0x0 0x100000>;
168 reg = <0x00 0x30e00000 0x00 0x1000>;
174 reg = <0x00 0x31f80000 0x00 0x200>;
183 reg = <0x00 0x31f81000 0x00 0x200>;
192 reg = <0x00 0x31f82000 0x00 0x200>;
201 reg = <0x00 0x31f83000 0x00 0x200>;
210 reg = <0x00 0x31f84000 0x00 0x200>;
219 reg = <0x00 0x31f85000 0x00 0x200>;
228 reg = <0x00 0x31f86000 0x00 0x200>;
237 reg = <0x00 0x31f87000 0x00 0x200>;
246 reg = <0x00 0x31f88000 0x00 0x200>;
255 reg = <0x00 0x31f89000 0x00 0x200>;
264 reg = <0x00 0x31f8a000 0x00 0x200>;
273 reg = <0x00 0x31f8b000 0x00 0x200>;
282 reg = <0x0 0x3c000000 0x0 0x400000>,
283 <0x0 0x38000000 0x0 0x400000>,
284 <0x0 0x31120000 0x0 0x100>,
285 <0x0 0x33000000 0x0 0x40000>;
288 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
296 reg = <0x0 0x31150000 0x0 0x100>,
297 <0x0 0x34000000 0x0 0x100000>,
298 <0x0 0x35000000 0x0 0x100000>;
307 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
308 <0x0f>, /* TX_HCHAN */
309 <0x10>; /* TX_UHCHAN */
310 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
311 <0x0b>, /* RX_HCHAN */
312 <0x0c>; /* RX_UHCHAN */
313 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
318 reg = <0x0 0x310d0000 0x0 0x400>;
331 reg = <0x0 0x4e00000 0x0 0x1200>;
335 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
337 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
338 <&main_udmap 0x4001>;
344 reg = <0x0 0x4e10000 0x0 0x7d>;
352 /* Proxy 0 addressing */
353 reg = <0x0 0x11c000 0x0 0x2b4>;
356 pinctrl-single,function-mask = <0xffffffff>;
366 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
370 ranges = <0x5000000 0x0 0x5000000 0x10000>;
374 #clock-cells = <0>;
380 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
381 #clock-cells = <0>;
383 assigned-clock-parents = <&k3_clks 292 0>;
387 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
388 #clock-cells = <0>;
395 #clock-cells = <0>;
400 #clock-cells = <0>;
406 reg = <0x5000000 0x10000>;
408 #size-cells = <0>;
410 resets = <&serdes_wiz0 0>;
426 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
430 ranges = <0x5010000 0x0 0x5010000 0x10000>;
434 #clock-cells = <0>;
440 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
441 #clock-cells = <0>;
443 assigned-clock-parents = <&k3_clks 293 0>;
447 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
448 #clock-cells = <0>;
455 #clock-cells = <0>;
460 #clock-cells = <0>;
466 reg = <0x5010000 0x10000>;
468 #size-cells = <0>;
470 resets = <&serdes_wiz1 0>;
486 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
490 ranges = <0x5020000 0x0 0x5020000 0x10000>;
494 #clock-cells = <0>;
500 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
501 #clock-cells = <0>;
503 assigned-clock-parents = <&k3_clks 294 0>;
507 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
508 #clock-cells = <0>;
515 #clock-cells = <0>;
520 #clock-cells = <0>;
526 reg = <0x5020000 0x10000>;
528 #size-cells = <0>;
530 resets = <&serdes_wiz2 0>;
546 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
550 ranges = <0x5030000 0x0 0x5030000 0x10000>;
554 #clock-cells = <0>;
560 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
561 #clock-cells = <0>;
563 assigned-clock-parents = <&k3_clks 295 0>;
567 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
568 #clock-cells = <0>;
575 #clock-cells = <0>;
580 #clock-cells = <0>;
586 reg = <0x5030000 0x10000>;
588 #size-cells = <0>;
590 resets = <&serdes_wiz3 0>;
601 reg = <0x00 0x02900000 0x00 0x1000>,
602 <0x00 0x02907000 0x00 0x400>,
603 <0x00 0x0d000000 0x00 0x00800000>,
604 <0x00 0x10000000 0x00 0x00001000>;
609 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
617 bus-range = <0x0 0xff>;
618 vendor-id = <0x104c>;
619 device-id = <0xb00d>;
620 msi-map = <0x0 &gic_its 0x0 0x10000>;
622 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
623 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
624 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
629 reg = <0x00 0x02900000 0x00 0x1000>,
630 <0x00 0x02907000 0x00 0x400>,
631 <0x00 0x0d000000 0x00 0x00800000>,
632 <0x00 0x10000000 0x00 0x08000000>;
636 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
643 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
649 reg = <0x00 0x02910000 0x00 0x1000>,
650 <0x00 0x02917000 0x00 0x400>,
651 <0x00 0x0d800000 0x00 0x00800000>,
652 <0x00 0x18000000 0x00 0x00001000>;
657 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
665 bus-range = <0x0 0xff>;
666 vendor-id = <0x104c>;
667 device-id = <0xb00d>;
668 msi-map = <0x0 &gic_its 0x10000 0x10000>;
670 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
671 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
672 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
677 reg = <0x00 0x02910000 0x00 0x1000>,
678 <0x00 0x02917000 0x00 0x400>,
679 <0x00 0x0d800000 0x00 0x00800000>,
680 <0x00 0x18000000 0x00 0x08000000>;
684 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
691 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
697 reg = <0x00 0x02920000 0x00 0x1000>,
698 <0x00 0x02927000 0x00 0x400>,
699 <0x00 0x0e000000 0x00 0x00800000>,
700 <0x44 0x00000000 0x00 0x00001000>;
705 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
713 bus-range = <0x0 0xff>;
714 vendor-id = <0x104c>;
715 device-id = <0xb00d>;
716 msi-map = <0x0 &gic_its 0x20000 0x10000>;
718 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
719 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
720 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
725 reg = <0x00 0x02920000 0x00 0x1000>,
726 <0x00 0x02927000 0x00 0x400>,
727 <0x00 0x0e000000 0x00 0x00800000>,
728 <0x44 0x00000000 0x00 0x08000000>;
732 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
739 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
745 reg = <0x00 0x02930000 0x00 0x1000>,
746 <0x00 0x02937000 0x00 0x400>,
747 <0x00 0x0e800000 0x00 0x00800000>,
748 <0x44 0x10000000 0x00 0x00001000>;
753 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
761 bus-range = <0x0 0xff>;
762 vendor-id = <0x104c>;
763 device-id = <0xb00d>;
764 msi-map = <0x0 &gic_its 0x30000 0x10000>;
766 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
767 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
768 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
773 reg = <0x00 0x02930000 0x00 0x1000>,
774 <0x00 0x02937000 0x00 0x400>,
775 <0x00 0x0e800000 0x00 0x00800000>,
776 <0x44 0x10000000 0x00 0x08000000>;
780 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
787 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
806 ranges = <0x05050000 0x00 0x05050000 0x010000>,
807 <0x0a030a00 0x00 0x0a030a00 0x40>;
815 reg = <0x05050000 0x010000>,
816 <0x0a030a00 0x40>; /* DPTX PHY */
819 resets = <&serdes_wiz4 0>;
830 #size-cells = <0>;
836 reg = <0x00 0x02800000 0x00 0x100>;
841 clocks = <&k3_clks 146 0>;
847 reg = <0x00 0x02810000 0x00 0x100>;
852 clocks = <&k3_clks 278 0>;
858 reg = <0x00 0x02820000 0x00 0x100>;
863 clocks = <&k3_clks 279 0>;
869 reg = <0x00 0x02830000 0x00 0x100>;
874 clocks = <&k3_clks 280 0>;
880 reg = <0x00 0x02840000 0x00 0x100>;
885 clocks = <&k3_clks 281 0>;
891 reg = <0x00 0x02850000 0x00 0x100>;
896 clocks = <&k3_clks 282 0>;
902 reg = <0x00 0x02860000 0x00 0x100>;
907 clocks = <&k3_clks 283 0>;
913 reg = <0x00 0x02870000 0x00 0x100>;
918 clocks = <&k3_clks 284 0>;
924 reg = <0x00 0x02880000 0x00 0x100>;
929 clocks = <&k3_clks 285 0>;
935 reg = <0x00 0x02890000 0x00 0x100>;
940 clocks = <&k3_clks 286 0>;
946 reg = <0x0 0x00600000 0x0 0x100>;
955 ti,davinci-gpio-unbanked = <0>;
957 clocks = <&k3_clks 105 0>;
963 reg = <0x0 0x00601000 0x0 0x100>;
971 ti,davinci-gpio-unbanked = <0>;
973 clocks = <&k3_clks 106 0>;
979 reg = <0x0 0x00610000 0x0 0x100>;
988 ti,davinci-gpio-unbanked = <0>;
990 clocks = <&k3_clks 107 0>;
996 reg = <0x0 0x00611000 0x0 0x100>;
1004 ti,davinci-gpio-unbanked = <0>;
1006 clocks = <&k3_clks 108 0>;
1012 reg = <0x0 0x00620000 0x0 0x100>;
1021 ti,davinci-gpio-unbanked = <0>;
1023 clocks = <&k3_clks 109 0>;
1029 reg = <0x0 0x00621000 0x0 0x100>;
1037 ti,davinci-gpio-unbanked = <0>;
1039 clocks = <&k3_clks 110 0>;
1045 reg = <0x0 0x00630000 0x0 0x100>;
1054 ti,davinci-gpio-unbanked = <0>;
1056 clocks = <&k3_clks 111 0>;
1062 reg = <0x0 0x00631000 0x0 0x100>;
1070 ti,davinci-gpio-unbanked = <0>;
1072 clocks = <&k3_clks 112 0>;
1078 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1082 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1088 ti,otap-del-sel-legacy = <0xf>;
1089 ti,otap-del-sel-mmc-hs = <0xf>;
1090 ti,otap-del-sel-ddr52 = <0x5>;
1091 ti,otap-del-sel-hs200 = <0x6>;
1092 ti,otap-del-sel-hs400 = <0x0>;
1093 ti,itap-del-sel-legacy = <0x10>;
1094 ti,itap-del-sel-mmc-hs = <0xa>;
1095 ti,itap-del-sel-ddr52 = <0x3>;
1096 ti,trm-icp = <0x8>;
1097 ti,strobe-sel = <0x77>;
1103 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1107 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1108 assigned-clocks = <&k3_clks 92 0>;
1110 ti,otap-del-sel-legacy = <0x0>;
1111 ti,otap-del-sel-sd-hs = <0xf>;
1112 ti,otap-del-sel-sdr12 = <0xf>;
1113 ti,otap-del-sel-sdr25 = <0xf>;
1114 ti,otap-del-sel-sdr50 = <0xc>;
1115 ti,otap-del-sel-ddr50 = <0xc>;
1116 ti,itap-del-sel-legacy = <0x0>;
1117 ti,itap-del-sel-sd-hs = <0x0>;
1118 ti,itap-del-sel-sdr12 = <0x0>;
1119 ti,itap-del-sel-sdr25 = <0x0>;
1120 ti,itap-del-sel-ddr50 = <0x2>;
1121 ti,trm-icp = <0x8>;
1122 ti,clkbuf-sel = <0x7>;
1124 sdhci-caps-mask = <0x2 0x0>;
1129 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1133 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1134 assigned-clocks = <&k3_clks 93 0>;
1136 ti,otap-del-sel-legacy = <0x0>;
1137 ti,otap-del-sel-sd-hs = <0xf>;
1138 ti,otap-del-sel-sdr12 = <0xf>;
1139 ti,otap-del-sel-sdr25 = <0xf>;
1140 ti,otap-del-sel-sdr50 = <0xc>;
1141 ti,otap-del-sel-ddr50 = <0xc>;
1142 ti,itap-del-sel-legacy = <0x0>;
1143 ti,itap-del-sel-sd-hs = <0x0>;
1144 ti,itap-del-sel-sdr12 = <0x0>;
1145 ti,itap-del-sel-sdr25 = <0x0>;
1146 ti,itap-del-sel-ddr50 = <0x2>;
1147 ti,trm-icp = <0x8>;
1148 ti,clkbuf-sel = <0x7>;
1150 sdhci-caps-mask = <0x2 0x0>;
1155 reg = <0x00 0x4104000 0x00 0x100>;
1168 reg = <0x00 0x6000000 0x00 0x10000>,
1169 <0x00 0x6010000 0x00 0x10000>,
1170 <0x00 0x6020000 0x00 0x10000>;
1172 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1174 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1185 reg = <0x00 0x4114000 0x00 0x100>;
1198 reg = <0x00 0x6400000 0x00 0x10000>,
1199 <0x00 0x6410000 0x00 0x10000>,
1200 <0x00 0x6420000 0x00 0x10000>;
1202 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1204 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1215 reg = <0x0 0x2000000 0x0 0x100>;
1218 #size-cells = <0>;
1220 clocks = <&k3_clks 187 0>;
1226 reg = <0x0 0x2010000 0x0 0x100>;
1229 #size-cells = <0>;
1231 clocks = <&k3_clks 188 0>;
1237 reg = <0x0 0x2020000 0x0 0x100>;
1240 #size-cells = <0>;
1242 clocks = <&k3_clks 189 0>;
1248 reg = <0x0 0x2030000 0x0 0x100>;
1251 #size-cells = <0>;
1253 clocks = <&k3_clks 190 0>;
1259 reg = <0x0 0x2040000 0x0 0x100>;
1262 #size-cells = <0>;
1264 clocks = <&k3_clks 191 0>;
1270 reg = <0x0 0x2050000 0x0 0x100>;
1273 #size-cells = <0>;
1275 clocks = <&k3_clks 192 0>;
1281 reg = <0x0 0x2060000 0x0 0x100>;
1284 #size-cells = <0>;
1286 clocks = <&k3_clks 193 0>;
1292 reg = <0x0 0x4e80000 0x0 0x100>;
1303 reg = <0x0 0x4e84000 0x0 0x10000>;
1306 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1318 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1319 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1331 #size-cells = <0>;
1333 port@0 {
1334 reg = <0>;
1346 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1347 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1348 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1349 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1351 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1352 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1353 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1354 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1356 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1357 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1358 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1359 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1361 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1362 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1363 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1364 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1365 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1374 clocks = <&k3_clks 152 0>,
1398 reg = <0x0 0x02b00000 0x0 0x2000>,
1399 <0x0 0x02b08000 0x0 0x1000>;
1405 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1415 reg = <0x0 0x02b10000 0x0 0x2000>,
1416 <0x0 0x02b18000 0x0 0x1000>;
1422 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1432 reg = <0x0 0x02b20000 0x0 0x2000>,
1433 <0x0 0x02b28000 0x0 0x1000>;
1439 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1449 reg = <0x0 0x02b30000 0x0 0x2000>,
1450 <0x0 0x02b38000 0x0 0x1000>;
1456 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1466 reg = <0x0 0x02b40000 0x0 0x2000>,
1467 <0x0 0x02b48000 0x0 0x1000>;
1473 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1483 reg = <0x0 0x02b50000 0x0 0x2000>,
1484 <0x0 0x02b58000 0x0 0x1000>;
1490 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1500 reg = <0x0 0x02b60000 0x0 0x2000>,
1501 <0x0 0x02b68000 0x0 0x1000>;
1507 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1517 reg = <0x0 0x02b70000 0x0 0x2000>,
1518 <0x0 0x02b78000 0x0 0x1000>;
1524 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1534 reg = <0x0 0x02b80000 0x0 0x2000>,
1535 <0x0 0x02b88000 0x0 0x1000>;
1541 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1551 reg = <0x0 0x02b90000 0x0 0x2000>,
1552 <0x0 0x02b98000 0x0 0x1000>;
1558 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1568 reg = <0x0 0x02ba0000 0x0 0x2000>,
1569 <0x0 0x02ba8000 0x0 0x1000>;
1575 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1585 reg = <0x0 0x02bb0000 0x0 0x2000>,
1586 <0x0 0x02bb8000 0x0 0x1000>;
1592 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1602 reg = <0x0 0x2200000 0x0 0x100>;
1611 reg = <0x0 0x2210000 0x0 0x100>;
1623 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1624 <0x5d00000 0x00 0x5d00000 0x20000>;
1629 reg = <0x5c00000 0x00008000>,
1630 <0x5c10000 0x00008000>;
1634 ti,sci-proc-ids = <0x06 0xff>;
1644 reg = <0x5d00000 0x00008000>,
1645 <0x5d10000 0x00008000>;
1649 ti,sci-proc-ids = <0x07 0xff>;
1663 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1664 <0x5f00000 0x00 0x5f00000 0x20000>;
1669 reg = <0x5e00000 0x00008000>,
1670 <0x5e10000 0x00008000>;
1674 ti,sci-proc-ids = <0x08 0xff>;
1684 reg = <0x5f00000 0x00008000>,
1685 <0x5f10000 0x00008000>;
1689 ti,sci-proc-ids = <0x09 0xff>;
1700 reg = <0x4d 0x80800000 0x00 0x00048000>,
1701 <0x4d 0x80e00000 0x00 0x00008000>,
1702 <0x4d 0x80f00000 0x00 0x00008000>;
1706 ti,sci-proc-ids = <0x03 0xff>;
1713 reg = <0x4d 0x81800000 0x00 0x00048000>,
1714 <0x4d 0x81e00000 0x00 0x00008000>,
1715 <0x4d 0x81f00000 0x00 0x00008000>;
1719 ti,sci-proc-ids = <0x04 0xff>;
1726 reg = <0x00 0x64800000 0x00 0x00080000>,
1727 <0x00 0x64e00000 0x00 0x0000c000>;
1731 ti,sci-proc-ids = <0x30 0xff>;
1738 reg = <0x00 0xb000000 0x00 0x80000>;
1742 ranges = <0x0 0x00 0x0b000000 0x100000>;
1744 icssg0_mem: memories@0 {
1745 reg = <0x0 0x2000>,
1746 <0x2000 0x2000>,
1747 <0x10000 0x10000>;
1754 reg = <0x26000 0x200>;
1757 ranges = <0x0 0x26000 0x2000>;
1761 #size-cells = <0>;
1764 reg = <0x3c>;
1765 #clock-cells = <0>;
1773 reg = <0x30>;
1774 #clock-cells = <0>;
1785 reg = <0x32000 0x100>;
1790 reg = <0x33000 0x1000>;
1795 reg = <0x20000 0x2000>;
1814 reg = <0x34000 0x3000>,
1815 <0x22000 0x100>,
1816 <0x22400 0x100>;
1823 reg = <0x4000 0x2000>,
1824 <0x23000 0x100>,
1825 <0x23400 0x100>;
1832 reg = <0xa000 0x1800>,
1833 <0x25000 0x100>,
1834 <0x25400 0x100>;
1841 reg = <0x38000 0x3000>,
1842 <0x24000 0x100>,
1843 <0x24400 0x100>;
1850 reg = <0x6000 0x2000>,
1851 <0x23800 0x100>,
1852 <0x23c00 0x100>;
1859 reg = <0xc000 0x1800>,
1860 <0x25800 0x100>,
1861 <0x25c00 0x100>;
1868 reg = <0x32400 0x100>;
1872 #size-cells = <0>;
1879 reg = <0x00 0xb100000 0x00 0x80000>;
1883 ranges = <0x0 0x00 0x0b100000 0x100000>;
1886 reg = <0x0 0x2000>,
1887 <0x2000 0x2000>,
1888 <0x10000 0x10000>;
1895 reg = <0x26000 0x200>;
1898 ranges = <0x0 0x26000 0x2000>;
1902 #size-cells = <0>;
1905 reg = <0x3c>;
1906 #clock-cells = <0>;
1914 reg = <0x30>;
1915 #clock-cells = <0>;
1926 reg = <0x32000 0x100>;
1931 reg = <0x33000 0x1000>;
1936 reg = <0x20000 0x2000>;
1955 reg = <0x34000 0x4000>,
1956 <0x22000 0x100>,
1957 <0x22400 0x100>;
1964 reg = <0x4000 0x2000>,
1965 <0x23000 0x100>,
1966 <0x23400 0x100>;
1973 reg = <0xa000 0x1800>,
1974 <0x25000 0x100>,
1975 <0x25400 0x100>;
1982 reg = <0x38000 0x4000>,
1983 <0x24000 0x100>,
1984 <0x24400 0x100>;
1991 reg = <0x6000 0x2000>,
1992 <0x23800 0x100>,
1993 <0x23c00 0x100>;
2000 reg = <0xc000 0x1800>,
2001 <0x25800 0x100>,
2002 <0x25c00 0x100>;
2009 reg = <0x32400 0x100>;
2013 #size-cells = <0>;
2020 reg = <0x00 0x02701000 0x00 0x200>,
2021 <0x00 0x02708000 0x00 0x8000>;
2024 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2029 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2034 reg = <0x00 0x02711000 0x00 0x200>,
2035 <0x00 0x02718000 0x00 0x8000>;
2038 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2043 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2048 reg = <0x00 0x02721000 0x00 0x200>,
2049 <0x00 0x02728000 0x00 0x8000>;
2052 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2057 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2062 reg = <0x00 0x02731000 0x00 0x200>,
2063 <0x00 0x02738000 0x00 0x8000>;
2066 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2071 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2076 reg = <0x00 0x02741000 0x00 0x200>,
2077 <0x00 0x02748000 0x00 0x8000>;
2080 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2085 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2090 reg = <0x00 0x02751000 0x00 0x200>,
2091 <0x00 0x02758000 0x00 0x8000>;
2094 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2099 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2104 reg = <0x00 0x02761000 0x00 0x200>,
2105 <0x00 0x02768000 0x00 0x8000>;
2108 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2113 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2118 reg = <0x00 0x02771000 0x00 0x200>,
2119 <0x00 0x02778000 0x00 0x8000>;
2122 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2127 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2132 reg = <0x00 0x02781000 0x00 0x200>,
2133 <0x00 0x02788000 0x00 0x8000>;
2136 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2141 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2146 reg = <0x00 0x02791000 0x00 0x200>,
2147 <0x00 0x02798000 0x00 0x8000>;
2150 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2155 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2160 reg = <0x00 0x027a1000 0x00 0x200>,
2161 <0x00 0x027a8000 0x00 0x8000>;
2164 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2169 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2174 reg = <0x00 0x027b1000 0x00 0x200>,
2175 <0x00 0x027b8000 0x00 0x8000>;
2178 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2183 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2188 reg = <0x00 0x027c1000 0x00 0x200>,
2189 <0x00 0x027c8000 0x00 0x8000>;
2192 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2197 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2202 reg = <0x00 0x027d1000 0x00 0x200>,
2203 <0x00 0x027d8000 0x00 0x8000>;
2206 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2211 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;