Lines Matching +full:wakeup +full:- +full:method

1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 	interrupt-parent = <&gic500>;
17 	#address-cells = <2>;
18 	#size-cells = <2>;
40 		#address-cells = <1>;
41 		#size-cells = <0>;
42 		cpu-map {
56 			compatible = "arm,cortex-a72";
59 			enable-method = "psci";
60 			i-cache-size = <0xc000>;
61 			i-cache-line-size = <64>;
62 			i-cache-sets = <256>;
63 			d-cache-size = <0x8000>;
64 			d-cache-line-size = <64>;
65 			d-cache-sets = <256>;
66 			next-level-cache = <&L2_0>;
70 			compatible = "arm,cortex-a72";
73 			enable-method = "psci";
74 			i-cache-size = <0xc000>;
75 			i-cache-line-size = <64>;
76 			i-cache-sets = <256>;
77 			d-cache-size = <0x8000>;
78 			d-cache-line-size = <64>;
79 			d-cache-sets = <256>;
80 			next-level-cache = <&L2_0>;
84 	L2_0: l2-cache0 {
86 		cache-level = <2>;
87 		cache-size = <0x100000>;
88 		cache-line-size = <64>;
89 		cache-sets = <1024>;
90 		next-level-cache = <&msmc_l3>;
93 	msmc_l3: l3-cache0 {
95 		cache-level = <3>;
100 			compatible = "linaro,optee-tz";
101 			method = "smc";
105 			compatible = "arm,psci-1.0";
106 			method = "smc";
110 	a72_timer0: timer-cl0-cpu0 {
111 		compatible = "arm,armv8-timer";
119 		compatible = "arm,cortex-a72-pmu";
124 		compatible = "simple-bus";
125 		#address-cells = <2>;
126 		#size-cells = <2>;
153 			compatible = "simple-bus";
154 			#address-cells = <2>;
155 			#size-cells = <2>;
174 #include "k3-j7200-main.dtsi"
175 #include "k3-j7200-mcu-wakeup.dtsi"