Lines Matching +full:sci +full:- +full:dev +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
26 k3_clks: clock-controller {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
38 compatible = "syscon", "simple-mfd";
40 #address-cells = <1>;
41 #size-cells = <1>;
45 compatible = "ti,am654-phy-gmii-sel";
47 #phy-cells = <1>;
52 compatible = "ti,am654-chipid";
57 compatible = "pinctrl-single";
60 #pinctrl-cells = <1>;
61 pinctrl-single,register-width = <32>;
62 pinctrl-single,function-mask = <0xffffffff>;
66 compatible = "mmio-sram";
69 #address-cells = <1>;
70 #size-cells = <1>;
74 compatible = "ti,j721e-uart", "ti,am654-uart";
77 clock-frequency = <48000000>;
78 current-speed = <115200>;
79 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
81 clock-names = "fclk";
85 compatible = "ti,j721e-uart", "ti,am654-uart";
88 clock-frequency = <96000000>;
89 current-speed = <115200>;
90 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
92 clock-names = "fclk";
95 wkup_gpio_intr: interrupt-controller@42200000 {
96 compatible = "ti,sci-intr";
98 ti,intr-trigger-type = <1>;
99 interrupt-controller;
100 interrupt-parent = <&gic500>;
101 #interrupt-cells = <1>;
102 ti,sci = <&dmsc>;
103 ti,sci-dev-id = <137>;
104 ti,interrupt-ranges = <16 960 16>;
108 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
110 gpio-controller;
111 #gpio-cells = <2>;
112 interrupt-parent = <&wkup_gpio_intr>;
114 interrupt-controller;
115 #interrupt-cells = <2>;
117 ti,davinci-gpio-unbanked = <0>;
118 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
120 clock-names = "gpio";
124 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-parent = <&wkup_gpio_intr>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
133 ti,davinci-gpio-unbanked = <0>;
134 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
136 clock-names = "gpio";
140 compatible = "simple-mfd";
141 #address-cells = <2>;
142 #size-cells = <2>;
144 dma-coherent;
145 dma-ranges;
146 ti,sci-dev-id = <232>;
149 compatible = "ti,am654-navss-ringacc";
154 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
155 ti,num-rings = <286>;
156 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
157 ti,sci = <&dmsc>;
158 ti,sci-dev-id = <235>;
159 msi-parent = <&main_udmass_inta>;
162 mcu_udmap: dma-controller@285c0000 {
163 compatible = "ti,j721e-navss-mcu-udmap";
167 reg-names = "gcfg", "rchanrt", "tchanrt";
168 msi-parent = <&main_udmass_inta>;
169 #dma-cells = <1>;
171 ti,sci = <&dmsc>;
172 ti,sci-dev-id = <236>;
175 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
177 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
179 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
184 compatible = "ti,j721e-cpsw-nuss";
185 #address-cells = <2>;
186 #size-cells = <2>;
188 reg-names = "cpsw_nuss";
190 dma-coherent;
192 clock-names = "fck";
193 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
204 dma-names = "tx0", "tx1", "tx2", "tx3",
208 ethernet-ports {
209 #address-cells = <1>;
210 #size-cells = <0>;
214 ti,mac-only;
216 ti,syscon-efuse = <&mcu_conf 0x200>;
222 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
224 #address-cells = <1>;
225 #size-cells = <0>;
227 clock-names = "fck";
232 compatible = "ti,am65-cpts";
235 clock-names = "cpts";
236 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-names = "cpts";
238 ti,cpts-ext-ts-inputs = <4>;
239 ti,cpts-periodic-outputs = <2>;
244 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
247 #address-cells = <1>;
248 #size-cells = <0>;
249 clock-names = "fck";
251 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
255 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 clock-names = "fck";
262 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
266 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
269 #address-cells = <1>;
270 #size-cells = <0>;
271 clock-names = "fck";
273 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
277 compatible = "syscon", "simple-mfd";
279 #address-cells = <2>;
280 #size-cells = <2>;
283 hbmc_mux: hbmc-mux {
284 compatible = "mmio-mux";
285 #mux-control-cells = <1>;
286 mux-reg-masks = <0x4 0x2>; /* HBMC select */
290 compatible = "ti,am654-hbmc";
293 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
295 assigned-clocks = <&k3_clks 102 5>;
296 assigned-clock-rates = <333333333>;
297 #address-cells = <2>;
298 #size-cells = <1>;
299 mux-controls = <&hbmc_mux 0>;
303 compatible = "ti,am654-ospi", "cdns,qspi-nor";
307 cdns,fifo-depth = <256>;
308 cdns,fifo-width = <4>;
309 cdns,trigger-address = <0x0>;
311 assigned-clocks = <&k3_clks 103 0>;
312 assigned-clock-parents = <&k3_clks 103 2>;
313 assigned-clock-rates = <166666666>;
314 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
315 #address-cells = <1>;
316 #size-cells = <0>;
321 compatible = "ti,am3359-tscadc";
324 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
326 assigned-clocks = <&k3_clks 0 3>;
327 assigned-clock-rates = <60000000>;
328 clock-names = "adc_tsc_fck";
331 dma-names = "fifo0", "fifo1";
334 #io-channel-cells = <1>;
335 compatible = "ti,am3359-adc";
340 compatible = "ti,j7200-r5fss";
341 ti,cluster-mode = <1>;
342 #address-cells = <1>;
343 #size-cells = <1>;
346 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
349 compatible = "ti,j7200-r5f";
352 reg-names = "atcm", "btcm";
353 ti,sci = <&dmsc>;
354 ti,sci-dev-id = <250>;
355 ti,sci-proc-ids = <0x01 0xff>;
357 firmware-name = "j7200-mcu-r5f0_0-fw";
358 ti,atcm-enable = <1>;
359 ti,btcm-enable = <1>;
364 compatible = "ti,j7200-r5f";
367 reg-names = "atcm", "btcm";
368 ti,sci = <&dmsc>;
369 ti,sci-dev-id = <251>;
370 ti,sci-proc-ids = <0x02 0xff>;
372 firmware-name = "j7200-mcu-r5f0_1-fw";
373 ti,atcm-enable = <1>;
374 ti,btcm-enable = <1>;
380 compatible = "ti,j721e-sa2ul";
382 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
383 #address-cells = <2>;
384 #size-cells = <2>;
388 dma-names = "tx", "rx1", "rx2";
389 dma-coherent;
392 compatible = "inside-secure,safexcel-eip76";
395 status = "disabled"; /* Used by OP-TEE */