Lines Matching +full:0 +full:x44083000
19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x40f00000 0x00 0x20000>;
42 ranges = <0x00 0x00 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x00 0x43000014 0x00 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
67 reg = <0x00 0x41c00000 0x00 0x100000>;
68 ranges = <0x00 0x00 0x41c00000 0x100000>;
75 reg = <0x00 0x42300000 0x00 0x100>;
86 reg = <0x00 0x40a00000 0x00 0x100>;
97 reg = <0x00 0x42200000 0x00 0x400>;
109 reg = <0x00 0x42110000 0x00 0x100>;
117 ti,davinci-gpio-unbanked = <0>;
119 clocks = <&k3_clks 113 0>;
125 reg = <0x00 0x42100000 0x00 0x100>;
133 ti,davinci-gpio-unbanked = <0>;
135 clocks = <&k3_clks 114 0>;
143 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
150 reg = <0x00 0x2b800000 0x00 0x400000>,
151 <0x00 0x2b000000 0x00 0x400000>,
152 <0x00 0x28590000 0x00 0x100>,
153 <0x00 0x2a500000 0x00 0x40000>;
156 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
164 reg = <0x00 0x285c0000 0x00 0x100>,
165 <0x00 0x2a800000 0x00 0x40000>,
166 <0x00 0x2aa00000 0x00 0x40000>;
175 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
176 <0x0f>; /* TX_HCHAN */
177 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
178 <0x0b>; /* RX_HCHAN */
179 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
187 reg = <0x00 0x46000000 0x00 0x200000>;
189 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
195 dmas = <&mcu_udmap 0xf000>,
196 <&mcu_udmap 0xf001>,
197 <&mcu_udmap 0xf002>,
198 <&mcu_udmap 0xf003>,
199 <&mcu_udmap 0xf004>,
200 <&mcu_udmap 0xf005>,
201 <&mcu_udmap 0xf006>,
202 <&mcu_udmap 0xf007>,
203 <&mcu_udmap 0x7000>;
210 #size-cells = <0>;
216 ti,syscon-efuse = <&mcu_conf 0x200>;
223 reg = <0x00 0xf00 0x00 0x100>;
225 #size-cells = <0>;
233 reg = <0x00 0x3d000 0x00 0x400>;
245 reg = <0x00 0x40b00000 0x00 0x100>;
248 #size-cells = <0>;
256 reg = <0x00 0x40b10000 0x00 0x100>;
259 #size-cells = <0>;
267 reg = <0x00 0x42120000 0x00 0x100>;
270 #size-cells = <0>;
278 reg = <0x00 0x47000000 0x00 0x100>;
286 mux-reg-masks = <0x4 0x2>; /* HBMC select */
291 reg = <0x00 0x47034000 0x00 0x100>,
292 <0x05 0x00000000 0x01 0x0000000>;
294 clocks = <&k3_clks 102 0>;
299 mux-controls = <&hbmc_mux 0>;
304 reg = <0x0 0x47040000 0x0 0x100>,
305 <0x5 0x00000000 0x1 0x0000000>;
309 cdns,trigger-address = <0x0>;
310 clocks = <&k3_clks 103 0>;
311 assigned-clocks = <&k3_clks 103 0>;
316 #size-cells = <0>;
322 reg = <0x00 0x40200000 0x00 0x1000>;
324 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
325 clocks = <&k3_clks 0 1>;
326 assigned-clocks = <&k3_clks 0 3>;
329 dmas = <&main_udmap 0x7400>,
330 <&main_udmap 0x7401>;
344 ranges = <0x41000000 0x00 0x41000000 0x20000>,
345 <0x41400000 0x00 0x41400000 0x20000>;
350 reg = <0x41000000 0x00010000>,
351 <0x41010000 0x00010000>;
355 ti,sci-proc-ids = <0x01 0xff>;
365 reg = <0x41400000 0x00008000>,
366 <0x41410000 0x00008000>;
370 ti,sci-proc-ids = <0x02 0xff>;
381 reg = <0x00 0x40900000 0x00 0x1200>;
385 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
386 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
387 <&mcu_udmap 0x7503>;
393 reg = <0x00 0x40910000 0x00 0x7d>;