Lines Matching +full:j7 +full:- +full:rti +full:- +full:wdt
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 serdes_ln_ctrl: mux-controller@4080 {
36 compatible = "mmio-mux";
37 #mux-control-cells = <1>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
42 usb_serdes_mux: mux-controller@4000 {
43 compatible = "mmio-mux";
44 #mux-control-cells = <1>;
45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
49 gic500: interrupt-controller@1800000 {
50 compatible = "arm,gic-v3";
51 #address-cells = <2>;
52 #size-cells = <2>;
54 #interrupt-cells = <3>;
55 interrupt-controller;
65 gic_its: msi-controller@1820000 {
66 compatible = "arm,gic-v3-its";
68 socionext,synquacer-pre-its = <0x1000000 0x400000>;
69 msi-controller;
70 #msi-cells = <1>;
74 main_gpio_intr: interrupt-controller@a00000 {
75 compatible = "ti,sci-intr";
77 ti,intr-trigger-type = <1>;
78 interrupt-controller;
79 interrupt-parent = <&gic500>;
80 #interrupt-cells = <1>;
82 ti,sci-dev-id = <131>;
83 ti,interrupt-ranges = <8 392 56>;
87 compatible = "simple-mfd";
88 #address-cells = <2>;
89 #size-cells = <2>;
91 ti,sci-dev-id = <199>;
92 dma-coherent;
93 dma-ranges;
95 main_navss_intr: interrupt-controller@310e0000 {
96 compatible = "ti,sci-intr";
98 ti,intr-trigger-type = <4>;
99 interrupt-controller;
100 interrupt-parent = <&gic500>;
101 #interrupt-cells = <1>;
103 ti,sci-dev-id = <213>;
104 ti,interrupt-ranges = <0 64 64>,
109 main_udmass_inta: msi-controller@33d00000 {
110 compatible = "ti,sci-inta";
112 interrupt-controller;
113 #interrupt-cells = <0>;
114 interrupt-parent = <&main_navss_intr>;
115 msi-controller;
117 ti,sci-dev-id = <209>;
118 ti,interrupt-ranges = <0 0 256>;
122 compatible = "ti,am654-secure-proxy";
123 #mbox-cells = <1>;
124 reg-names = "target_data", "rt", "scfg";
128 interrupt-names = "rx_011";
133 compatible = "ti,am654-hwspinlock";
135 #hwlock-cells = <1>;
139 compatible = "ti,am654-mailbox";
141 #mbox-cells = <1>;
142 ti,mbox-num-users = <4>;
143 ti,mbox-num-fifos = <16>;
144 interrupt-parent = <&main_navss_intr>;
148 compatible = "ti,am654-mailbox";
150 #mbox-cells = <1>;
151 ti,mbox-num-users = <4>;
152 ti,mbox-num-fifos = <16>;
153 interrupt-parent = <&main_navss_intr>;
157 compatible = "ti,am654-mailbox";
159 #mbox-cells = <1>;
160 ti,mbox-num-users = <4>;
161 ti,mbox-num-fifos = <16>;
162 interrupt-parent = <&main_navss_intr>;
166 compatible = "ti,am654-mailbox";
168 #mbox-cells = <1>;
169 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <16>;
171 interrupt-parent = <&main_navss_intr>;
175 compatible = "ti,am654-mailbox";
177 #mbox-cells = <1>;
178 ti,mbox-num-users = <4>;
179 ti,mbox-num-fifos = <16>;
180 interrupt-parent = <&main_navss_intr>;
184 compatible = "ti,am654-mailbox";
186 #mbox-cells = <1>;
187 ti,mbox-num-users = <4>;
188 ti,mbox-num-fifos = <16>;
189 interrupt-parent = <&main_navss_intr>;
193 compatible = "ti,am654-mailbox";
195 #mbox-cells = <1>;
196 ti,mbox-num-users = <4>;
197 ti,mbox-num-fifos = <16>;
198 interrupt-parent = <&main_navss_intr>;
202 compatible = "ti,am654-mailbox";
204 #mbox-cells = <1>;
205 ti,mbox-num-users = <4>;
206 ti,mbox-num-fifos = <16>;
207 interrupt-parent = <&main_navss_intr>;
211 compatible = "ti,am654-mailbox";
213 #mbox-cells = <1>;
214 ti,mbox-num-users = <4>;
215 ti,mbox-num-fifos = <16>;
216 interrupt-parent = <&main_navss_intr>;
220 compatible = "ti,am654-mailbox";
222 #mbox-cells = <1>;
223 ti,mbox-num-users = <4>;
224 ti,mbox-num-fifos = <16>;
225 interrupt-parent = <&main_navss_intr>;
229 compatible = "ti,am654-mailbox";
231 #mbox-cells = <1>;
232 ti,mbox-num-users = <4>;
233 ti,mbox-num-fifos = <16>;
234 interrupt-parent = <&main_navss_intr>;
238 compatible = "ti,am654-mailbox";
240 #mbox-cells = <1>;
241 ti,mbox-num-users = <4>;
242 ti,mbox-num-fifos = <16>;
243 interrupt-parent = <&main_navss_intr>;
247 compatible = "ti,am654-navss-ringacc";
252 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
253 ti,num-rings = <1024>;
254 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
256 ti,sci-dev-id = <211>;
257 msi-parent = <&main_udmass_inta>;
260 main_udmap: dma-controller@31150000 {
261 compatible = "ti,j721e-navss-main-udmap";
265 reg-names = "gcfg", "rchanrt", "tchanrt";
266 msi-parent = <&main_udmass_inta>;
267 #dma-cells = <1>;
270 ti,sci-dev-id = <212>;
273 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
276 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
279 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
283 compatible = "ti,j721e-cpts";
285 reg-names = "cpts";
287 clock-names = "cpts";
288 interrupts-extended = <&main_navss_intr 391>;
289 interrupt-names = "cpts";
290 ti,cpts-periodic-outputs = <6>;
291 ti,cpts-ext-ts-inputs = <8>;
296 compatible = "pinctrl-single";
299 #pinctrl-cells = <1>;
300 pinctrl-single,register-width = <32>;
301 pinctrl-single,function-mask = <0xffffffff>;
305 compatible = "pinctrl-single";
308 #pinctrl-cells = <1>;
309 pinctrl-single,register-width = <32>;
310 pinctrl-single,function-mask = <0xffffffff>;
314 compatible = "ti,j721e-uart", "ti,am654-uart";
317 clock-frequency = <48000000>;
318 current-speed = <115200>;
319 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
321 clock-names = "fclk";
325 compatible = "ti,j721e-uart", "ti,am654-uart";
328 clock-frequency = <48000000>;
329 current-speed = <115200>;
330 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
332 clock-names = "fclk";
336 compatible = "ti,j721e-uart", "ti,am654-uart";
339 clock-frequency = <48000000>;
340 current-speed = <115200>;
341 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
343 clock-names = "fclk";
347 compatible = "ti,j721e-uart", "ti,am654-uart";
350 clock-frequency = <48000000>;
351 current-speed = <115200>;
352 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
354 clock-names = "fclk";
358 compatible = "ti,j721e-uart", "ti,am654-uart";
361 clock-frequency = <48000000>;
362 current-speed = <115200>;
363 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
365 clock-names = "fclk";
369 compatible = "ti,j721e-uart", "ti,am654-uart";
372 clock-frequency = <48000000>;
373 current-speed = <115200>;
374 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
376 clock-names = "fclk";
380 compatible = "ti,j721e-uart", "ti,am654-uart";
383 clock-frequency = <48000000>;
384 current-speed = <115200>;
385 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
387 clock-names = "fclk";
391 compatible = "ti,j721e-uart", "ti,am654-uart";
394 clock-frequency = <48000000>;
395 current-speed = <115200>;
396 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
398 clock-names = "fclk";
402 compatible = "ti,j721e-uart", "ti,am654-uart";
405 clock-frequency = <48000000>;
406 current-speed = <115200>;
407 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
409 clock-names = "fclk";
413 compatible = "ti,j721e-uart", "ti,am654-uart";
416 clock-frequency = <48000000>;
417 current-speed = <115200>;
418 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
420 clock-names = "fclk";
424 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
427 #address-cells = <1>;
428 #size-cells = <0>;
429 clock-names = "fck";
431 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
435 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
438 #address-cells = <1>;
439 #size-cells = <0>;
440 clock-names = "fck";
442 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
446 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
449 #address-cells = <1>;
450 #size-cells = <0>;
451 clock-names = "fck";
453 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
457 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 clock-names = "fck";
464 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
468 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clock-names = "fck";
475 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
479 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clock-names = "fck";
486 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
490 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
493 #address-cells = <1>;
494 #size-cells = <0>;
495 clock-names = "fck";
497 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
501 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
504 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
505 clock-names = "clk_ahb", "clk_xin";
507 ti,otap-del-sel-legacy = <0x0>;
508 ti,otap-del-sel-mmc-hs = <0x0>;
509 ti,otap-del-sel-ddr52 = <0x6>;
510 ti,otap-del-sel-hs200 = <0x8>;
511 ti,otap-del-sel-hs400 = <0x5>;
512 ti,itap-del-sel-legacy = <0x10>;
513 ti,itap-del-sel-mmc-hs = <0xa>;
514 ti,strobe-sel = <0x77>;
515 ti,clkbuf-sel = <0x7>;
516 ti,trm-icp = <0x8>;
517 bus-width = <8>;
518 mmc-ddr-1_8v;
519 mmc-hs200-1_8v;
520 mmc-hs400-1_8v;
521 dma-coherent;
525 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
528 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
529 clock-names = "clk_ahb", "clk_xin";
531 ti,otap-del-sel-legacy = <0x0>;
532 ti,otap-del-sel-sd-hs = <0x0>;
533 ti,otap-del-sel-sdr12 = <0xf>;
534 ti,otap-del-sel-sdr25 = <0xf>;
535 ti,otap-del-sel-sdr50 = <0xc>;
536 ti,otap-del-sel-sdr104 = <0x5>;
537 ti,otap-del-sel-ddr50 = <0xc>;
538 ti,itap-del-sel-legacy = <0x0>;
539 ti,itap-del-sel-sd-hs = <0x0>;
540 ti,itap-del-sel-sdr12 = <0x0>;
541 ti,itap-del-sel-sdr25 = <0x0>;
542 ti,clkbuf-sel = <0x7>;
543 ti,trm-icp = <0x8>;
544 dma-coherent;
548 compatible = "ti,j721e-wiz-10g";
549 #address-cells = <1>;
550 #size-cells = <1>;
551 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
553 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
554 num-lanes = <4>;
555 #reset-cells = <1>;
558 assigned-clocks = <&k3_clks 292 85>;
559 assigned-clock-parents = <&k3_clks 292 89>;
561 wiz0_pll0_refclk: pll0-refclk {
563 clock-output-names = "wiz0_pll0_refclk";
564 #clock-cells = <0>;
565 assigned-clocks = <&wiz0_pll0_refclk>;
566 assigned-clock-parents = <&k3_clks 292 85>;
569 wiz0_pll1_refclk: pll1-refclk {
571 clock-output-names = "wiz0_pll1_refclk";
572 #clock-cells = <0>;
573 assigned-clocks = <&wiz0_pll1_refclk>;
574 assigned-clock-parents = <&k3_clks 292 85>;
577 wiz0_refclk_dig: refclk-dig {
579 clock-output-names = "wiz0_refclk_dig";
580 #clock-cells = <0>;
581 assigned-clocks = <&wiz0_refclk_dig>;
582 assigned-clock-parents = <&k3_clks 292 85>;
585 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
587 #clock-cells = <0>;
591 compatible = "ti,j721e-serdes-10g";
593 reg-names = "torrent_phy";
595 reset-names = "torrent_reset";
597 clock-names = "refclk";
598 #address-cells = <1>;
599 #size-cells = <0>;
604 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
609 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
610 interrupt-names = "link_state";
613 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
614 max-link-speed = <3>;
615 num-lanes = <4>;
616 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
618 clock-names = "fck";
619 #address-cells = <3>;
620 #size-cells = <2>;
621 bus-range = <0x0 0xff>;
622 cdns,no-bar-match-nbits = <64>;
623 vendor-id = <0x104c>;
624 device-id = <0xb00f>;
625 msi-map = <0x0 &gic_its 0x0 0x10000>;
626 dma-coherent;
629 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
632 pcie1_ep: pcie-ep@2910000 {
633 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
638 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
639 interrupt-names = "link_state";
641 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
642 max-link-speed = <3>;
643 num-lanes = <4>;
644 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
646 clock-names = "fck";
647 max-functions = /bits/ 8 <6>;
648 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
649 dma-coherent;
652 usbss0: cdns-usb@4104000 {
653 compatible = "ti,j721e-usb";
655 dma-coherent;
656 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
658 clock-names = "ref", "lpm";
659 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
660 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
661 #address-cells = <2>;
662 #size-cells = <2>;
670 reg-names = "otg", "xhci", "dev";
674 interrupt-names = "host",
677 maximum-speed = "super-speed";
679 cdns,phyrst-a-enable;
684 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
686 gpio-controller;
687 #gpio-cells = <2>;
688 interrupt-parent = <&main_gpio_intr>;
691 interrupt-controller;
692 #interrupt-cells = <2>;
694 ti,davinci-gpio-unbanked = <0>;
695 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
697 clock-names = "gpio";
701 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
703 gpio-controller;
704 #gpio-cells = <2>;
705 interrupt-parent = <&main_gpio_intr>;
708 interrupt-controller;
709 #interrupt-cells = <2>;
711 ti,davinci-gpio-unbanked = <0>;
712 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
714 clock-names = "gpio";
718 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
720 gpio-controller;
721 #gpio-cells = <2>;
722 interrupt-parent = <&main_gpio_intr>;
725 interrupt-controller;
726 #interrupt-cells = <2>;
728 ti,davinci-gpio-unbanked = <0>;
729 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
731 clock-names = "gpio";
735 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
737 gpio-controller;
738 #gpio-cells = <2>;
739 interrupt-parent = <&main_gpio_intr>;
742 interrupt-controller;
743 #interrupt-cells = <2>;
745 ti,davinci-gpio-unbanked = <0>;
746 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
748 clock-names = "gpio";
752 compatible = "ti,j7-rti-wdt";
755 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
756 assigned-clocks = <&k3_clks 252 1>;
757 assigned-clock-parents = <&k3_clks 252 5>;
761 compatible = "ti,j7-rti-wdt";
764 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
765 assigned-clocks = <&k3_clks 253 1>;
766 assigned-clock-parents = <&k3_clks 253 5>;
770 compatible = "ti,j7200-r5fss";
771 ti,cluster-mode = <1>;
772 #address-cells = <1>;
773 #size-cells = <1>;
776 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
779 compatible = "ti,j7200-r5f";
782 reg-names = "atcm", "btcm";
784 ti,sci-dev-id = <245>;
785 ti,sci-proc-ids = <0x06 0xff>;
787 firmware-name = "j7200-main-r5f0_0-fw";
788 ti,atcm-enable = <1>;
789 ti,btcm-enable = <1>;
794 compatible = "ti,j7200-r5f";
797 reg-names = "atcm", "btcm";
799 ti,sci-dev-id = <246>;
800 ti,sci-proc-ids = <0x07 0xff>;
802 firmware-name = "j7200-main-r5f0_1-fw";
803 ti,atcm-enable = <1>;
804 ti,btcm-enable = <1>;