Lines Matching +full:0 +full:x7fef000
10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
56 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
57 <0x00 0x01900000 0x00 0x100000>, /* GICR */
58 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
59 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
60 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
67 reg = <0x00 0x01820000 0x00 0x10000>;
68 socionext,synquacer-pre-its = <0x1000000 0x400000>;
76 reg = <0x00 0x00a00000 0x00 0x800>;
90 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
97 reg = <0x00 0x310e0000 0x00 0x4000>;
104 ti,interrupt-ranges = <0 64 64>,
111 reg = <0x00 0x33d00000 0x00 0x100000>;
113 #interrupt-cells = <0>;
118 ti,interrupt-ranges = <0 0 256>;
125 reg = <0x00 0x32c00000 0x00 0x100000>,
126 <0x00 0x32400000 0x00 0x100000>,
127 <0x00 0x32800000 0x00 0x100000>;
134 reg = <0x00 0x30e00000 0x00 0x1000>;
140 reg = <0x00 0x31f80000 0x00 0x200>;
149 reg = <0x00 0x31f81000 0x00 0x200>;
158 reg = <0x00 0x31f82000 0x00 0x200>;
167 reg = <0x00 0x31f83000 0x00 0x200>;
176 reg = <0x00 0x31f84000 0x00 0x200>;
185 reg = <0x00 0x31f85000 0x00 0x200>;
194 reg = <0x00 0x31f86000 0x00 0x200>;
203 reg = <0x00 0x31f87000 0x00 0x200>;
212 reg = <0x00 0x31f88000 0x00 0x200>;
221 reg = <0x00 0x31f89000 0x00 0x200>;
230 reg = <0x00 0x31f8a000 0x00 0x200>;
239 reg = <0x00 0x31f8b000 0x00 0x200>;
248 reg = <0x00 0x3c000000 0x00 0x400000>,
249 <0x00 0x38000000 0x00 0x400000>,
250 <0x00 0x31120000 0x00 0x100>,
251 <0x00 0x33000000 0x00 0x40000>;
254 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
262 reg = <0x00 0x31150000 0x00 0x100>,
263 <0x00 0x34000000 0x00 0x100000>,
264 <0x00 0x35000000 0x00 0x100000>;
273 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
274 <0x0f>, /* TX_HCHAN */
275 <0x10>; /* TX_UHCHAN */
276 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
277 <0x0b>, /* RX_HCHAN */
278 <0x0c>; /* RX_UHCHAN */
279 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
284 reg = <0x00 0x310d0000 0x00 0x400>;
297 /* Proxy 0 addressing */
298 reg = <0x00 0x11c000 0x00 0x10c>;
301 pinctrl-single,function-mask = <0xffffffff>;
306 /* Proxy 0 addressing */
307 reg = <0x00 0x11c11c 0x00 0xc>;
310 pinctrl-single,function-mask = <0xffffffff>;
315 reg = <0x00 0x02800000 0x00 0x100>;
326 reg = <0x00 0x02810000 0x00 0x100>;
337 reg = <0x00 0x02820000 0x00 0x100>;
348 reg = <0x00 0x02830000 0x00 0x100>;
359 reg = <0x00 0x02840000 0x00 0x100>;
370 reg = <0x00 0x02850000 0x00 0x100>;
381 reg = <0x00 0x02860000 0x00 0x100>;
392 reg = <0x00 0x02870000 0x00 0x100>;
403 reg = <0x00 0x02880000 0x00 0x100>;
414 reg = <0x00 0x02890000 0x00 0x100>;
425 reg = <0x00 0x2000000 0x00 0x100>;
428 #size-cells = <0>;
436 reg = <0x00 0x2010000 0x00 0x100>;
439 #size-cells = <0>;
447 reg = <0x00 0x2020000 0x00 0x100>;
450 #size-cells = <0>;
458 reg = <0x00 0x2030000 0x00 0x100>;
461 #size-cells = <0>;
469 reg = <0x00 0x2040000 0x00 0x100>;
472 #size-cells = <0>;
480 reg = <0x00 0x2050000 0x00 0x100>;
483 #size-cells = <0>;
491 reg = <0x00 0x2060000 0x00 0x100>;
494 #size-cells = <0>;
502 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
506 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
507 ti,otap-del-sel-legacy = <0x0>;
508 ti,otap-del-sel-mmc-hs = <0x0>;
509 ti,otap-del-sel-ddr52 = <0x6>;
510 ti,otap-del-sel-hs200 = <0x8>;
511 ti,otap-del-sel-hs400 = <0x5>;
512 ti,itap-del-sel-legacy = <0x10>;
513 ti,itap-del-sel-mmc-hs = <0xa>;
514 ti,strobe-sel = <0x77>;
515 ti,clkbuf-sel = <0x7>;
516 ti,trm-icp = <0x8>;
526 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
531 ti,otap-del-sel-legacy = <0x0>;
532 ti,otap-del-sel-sd-hs = <0x0>;
533 ti,otap-del-sel-sdr12 = <0xf>;
534 ti,otap-del-sel-sdr25 = <0xf>;
535 ti,otap-del-sel-sdr50 = <0xc>;
536 ti,otap-del-sel-sdr104 = <0x5>;
537 ti,otap-del-sel-ddr50 = <0xc>;
538 ti,itap-del-sel-legacy = <0x0>;
539 ti,itap-del-sel-sd-hs = <0x0>;
540 ti,itap-del-sel-sdr12 = <0x0>;
541 ti,itap-del-sel-sdr25 = <0x0>;
542 ti,clkbuf-sel = <0x7>;
543 ti,trm-icp = <0x8>;
556 ranges = <0x5060000 0x0 0x5060000 0x10000>;
564 #clock-cells = <0>;
572 #clock-cells = <0>;
580 #clock-cells = <0>;
587 #clock-cells = <0>;
592 reg = <0x05060000 0x00010000>;
594 resets = <&serdes_wiz0 0>;
599 #size-cells = <0>;
605 reg = <0x00 0x02910000 0x00 0x1000>,
606 <0x00 0x02917000 0x00 0x400>,
607 <0x00 0x0d800000 0x00 0x00800000>,
608 <0x00 0x18000000 0x00 0x00001000>;
613 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
621 bus-range = <0x0 0xff>;
623 vendor-id = <0x104c>;
624 device-id = <0xb00f>;
625 msi-map = <0x0 &gic_its 0x0 0x10000>;
627 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
628 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
629 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
634 reg = <0x00 0x02910000 0x00 0x1000>,
635 <0x00 0x02917000 0x00 0x400>,
636 <0x00 0x0d800000 0x00 0x00800000>,
637 <0x00 0x18000000 0x00 0x08000000>;
641 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
648 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
654 reg = <0x00 0x4104000 0x00 0x100>;
667 reg = <0x00 0x6000000 0x00 0x10000>,
668 <0x00 0x6010000 0x00 0x10000>,
669 <0x00 0x6020000 0x00 0x10000>;
671 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
673 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
685 reg = <0x00 0x00600000 0x00 0x100>;
694 ti,davinci-gpio-unbanked = <0>;
696 clocks = <&k3_clks 105 0>;
702 reg = <0x00 0x00610000 0x00 0x100>;
711 ti,davinci-gpio-unbanked = <0>;
713 clocks = <&k3_clks 107 0>;
719 reg = <0x00 0x00620000 0x00 0x100>;
728 ti,davinci-gpio-unbanked = <0>;
730 clocks = <&k3_clks 109 0>;
736 reg = <0x00 0x00630000 0x00 0x100>;
745 ti,davinci-gpio-unbanked = <0>;
747 clocks = <&k3_clks 111 0>;
753 reg = <0x0 0x2200000 0x0 0x100>;
762 reg = <0x0 0x2210000 0x0 0x100>;
774 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
775 <0x5d00000 0x00 0x5d00000 0x20000>;
780 reg = <0x5c00000 0x00010000>,
781 <0x5c10000 0x00010000>;
785 ti,sci-proc-ids = <0x06 0xff>;
795 reg = <0x5d00000 0x00008000>,
796 <0x5d10000 0x00008000>;
800 ti,sci-proc-ids = <0x07 0xff>;