Lines Matching +full:j721e +full:- +full:cpb
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/mux/ti-serdes.h>
12 #include <dt-bindings/phy/phy.h>
15 compatible = "ti,j7200-evm", "ti,j7200";
19 stdout-path = "serial2:115200n8";
23 evm_12v0: fixedregulator-evm12v0 {
25 compatible = "regulator-fixed";
26 regulator-name = "evm_12v0";
27 regulator-min-microvolt = <12000000>;
28 regulator-max-microvolt = <12000000>;
29 regulator-always-on;
30 regulator-boot-on;
33 vsys_3v3: fixedregulator-vsys3v3 {
35 compatible = "regulator-fixed";
36 regulator-name = "vsys_3v3";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 vin-supply = <&evm_12v0>;
40 regulator-always-on;
41 regulator-boot-on;
44 vsys_5v0: fixedregulator-vsys5v0 {
46 compatible = "regulator-fixed";
47 regulator-name = "vsys_5v0";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 vin-supply = <&evm_12v0>;
51 regulator-always-on;
52 regulator-boot-on;
55 vdd_mmc1: fixedregulator-sd {
57 compatible = "regulator-fixed";
58 regulator-name = "vdd_mmc1";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 regulator-boot-on;
62 enable-active-high;
63 vin-supply = <&vsys_3v3>;
67 vdd_sd_dv: gpio-regulator-TLV71033 {
69 compatible = "regulator-gpio";
70 regulator-name = "tlv71033";
71 pinctrl-names = "default";
72 pinctrl-0 = <&vdd_sd_dv_pins_default>;
73 regulator-min-microvolt = <1800000>;
74 regulator-max-microvolt = <3300000>;
75 regulator-boot-on;
76 vin-supply = <&vsys_5v0>;
84 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
85 pinctrl-single,pins = <
101 mcu_mdio_pins_default: mcu-mdio1-pins-default {
102 pinctrl-single,pins = <
110 main_i2c0_pins_default: main-i2c0-pins-default {
111 pinctrl-single,pins = <
117 main_i2c1_pins_default: main-i2c1-pins-default {
118 pinctrl-single,pins = <
124 main_mmc1_pins_default: main-mmc1-pins-default {
125 pinctrl-single,pins = <
137 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
138 pinctrl-single,pins = <
145 main_usbss0_pins_default: main-usbss0-pins-default {
146 pinctrl-single,pins = <
159 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
224 phy0: ethernet-phy@0 {
226 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
227 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
232 phy-mode = "rgmii-rxid";
233 phy-handle = <&phy0>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&main_i2c0_pins_default>;
239 clock-frequency = <400000>;
244 gpio-controller;
245 #gpio-cells = <2>;
251 gpio-controller;
252 #gpio-cells = <2>;
257 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
258 * swapped on the CPB.
260 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
261 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
264 pinctrl-names = "default";
265 pinctrl-0 = <&main_i2c1_pins_default>;
266 clock-frequency = <400000>;
271 gpio-controller;
272 #gpio-cells = <2>;
273 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
281 non-removable;
282 ti,driver-strength-ohm = <50>;
283 disable-wp;
288 pinctrl-0 = <&main_mmc1_pins_default>;
289 pinctrl-names = "default";
290 vmmc-supply = <&vdd_mmc1>;
291 vqmmc-supply = <&vdd_sd_dv>;
292 ti,driver-strength-ohm = <50>;
293 disable-wp;
297 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
302 idle-states = <1>; /* USB0 to SERDES lane 3 */
306 pinctrl-names = "default";
307 pinctrl-0 = <&main_usbss0_pins_default>;
308 ti,vbus-divider;
309 ti,usb2-only;
314 maximum-speed = "high-speed";
319 ti,adc-channels = <0 1 2 3 4 5 6 7>;
324 clock-frequency = <100000000>;
330 cdns,num-lanes = <2>;
331 #phy-cells = <0>;
332 cdns,phy-type = <PHY_TYPE_PCIE>;
338 cdns,num-lanes = <1>;
339 #phy-cells = <0>;
340 cdns,phy-type = <PHY_TYPE_QSGMII>;
346 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
348 phy-names = "pcie-phy";
349 num-lanes = <2>;
354 phy-names = "pcie-phy";
355 num-lanes = <2>;