Lines Matching +full:0 +full:x41000000
11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
25 reg = <0x00 0x40a00000 0x00 0x100>;
34 reg = <0x00 0x41c00000 0x00 0x80000>;
35 ranges = <0x0 0x00 0x41c00000 0x80000>;
42 reg = <0x0 0x40b00000 0x0 0x100>;
45 #size-cells = <0>;
53 reg = <0x0 0x40300000 0x0 0x400>;
58 #size-cells = <0>;
63 reg = <0x0 0x40310000 0x0 0x400>;
68 #size-cells = <0>;
73 reg = <0x0 0x40320000 0x0 0x400>;
78 #size-cells = <0>;
83 reg = <0x0 0x40200000 0x0 0x1000>;
85 clocks = <&k3_clks 0 2>;
86 assigned-clocks = <&k3_clks 0 2>;
89 dmas = <&mcu_udmap 0x7100>,
90 <&mcu_udmap 0x7101 >;
101 reg = <0x0 0x40210000 0x0 0x1000>;
107 dmas = <&mcu_udmap 0x7102>,
108 <&mcu_udmap 0x7103>;
121 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
129 reg = <0x0 0x2b800000 0x0 0x400000>,
130 <0x0 0x2b000000 0x0 0x400000>,
131 <0x0 0x28590000 0x0 0x100>,
132 <0x0 0x2a500000 0x0 0x40000>;
135 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
143 reg = <0x0 0x285c0000 0x0 0x100>,
144 <0x0 0x2a800000 0x0 0x40000>,
145 <0x0 0x2aa00000 0x0 0x40000>;
154 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
155 <0xd>; /* TX_CHAN */
156 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
157 <0xa>; /* RX_CHAN */
158 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
164 reg = <0x0 0x40528000 0x0 0x400>,
165 <0x0 0x40500000 0x0 0x4400>;
168 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
174 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
179 reg = <0x0 0x40568000 0x0 0x400>,
180 <0x0 0x40540000 0x0 0x4400>;
183 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
189 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
200 reg = <0x0 0x47040000 0x0 0x100>,
201 <0x5 0x00000000 0x1 0x0000000>;
205 cdns,trigger-address = <0x0>;
206 clocks = <&k3_clks 248 0>;
207 assigned-clocks = <&k3_clks 248 0>;
212 #size-cells = <0>;
217 reg = <0x0 0x47050000 0x0 0x100>,
218 <0x7 0x00000000 0x1 0x00000000>;
222 cdns,trigger-address = <0x0>;
226 #size-cells = <0>;
234 reg = <0x0 0x46000000 0x0 0x200000>;
236 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
242 dmas = <&mcu_udmap 0xf000>,
243 <&mcu_udmap 0xf001>,
244 <&mcu_udmap 0xf002>,
245 <&mcu_udmap 0xf003>,
246 <&mcu_udmap 0xf004>,
247 <&mcu_udmap 0xf005>,
248 <&mcu_udmap 0xf006>,
249 <&mcu_udmap 0xf007>,
250 <&mcu_udmap 0x7000>;
257 #size-cells = <0>;
263 ti,syscon-efuse = <&mcu_conf 0x200>;
270 reg = <0x0 0xf00 0x0 0x100>;
272 #size-cells = <0>;
280 reg = <0x0 0x3d000 0x0 0x400>;
289 #clock-cells = <0>;
305 ranges = <0x41000000 0x00 0x41000000 0x20000>,
306 <0x41400000 0x00 0x41400000 0x20000>;
311 reg = <0x41000000 0x00008000>,
312 <0x41010000 0x00008000>;
316 ti,sci-proc-ids = <0x01 0xff>;
326 reg = <0x41400000 0x00008000>,
327 <0x41410000 0x00008000>;
331 ti,sci-proc-ids = <0x02 0xff>;
342 reg = <0x0 0x40610000 0x0 0x100>;
343 clocks = <&k3_clks 135 0>;
345 assigned-clocks = <&k3_clks 135 0>;