Lines Matching +full:0 +full:x100
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
59 reg = <0x0 0x900000 0x0 0x2000>;
69 mux-controls = <&serdes_mux 0>;
74 reg = <0x0 0x910000 0x0 0x2000>;
89 reg = <0x00 0x02800000 0x00 0x100>;
98 reg = <0x00 0x02810000 0x00 0x100>;
106 reg = <0x00 0x02820000 0x00 0x100>;
114 reg = <0x0 0x4e00000 0x0 0x1200>;
118 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
120 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
121 <&main_udmap 0x4003>;
127 reg = <0x0 0x4e10000 0x0 0x7d>;
136 reg = <0x0 0x11c000 0x0 0x2e4>;
139 pinctrl-single,function-mask = <0xffffffff>;
144 reg = <0x0 0x11c2e8 0x0 0x24>;
147 pinctrl-single,function-mask = <0xffffffff>;
152 reg = <0x0 0x2000000 0x0 0x100>;
155 #size-cells = <0>;
163 reg = <0x0 0x2010000 0x0 0x100>;
166 #size-cells = <0>;
174 reg = <0x0 0x2020000 0x0 0x100>;
177 #size-cells = <0>;
185 reg = <0x0 0x2030000 0x0 0x100>;
188 #size-cells = <0>;
197 reg = <0x0 0x03100000 0x0 0x60>;
199 clocks = <&k3_clks 39 0>;
205 reg = <0x0 0x2100000 0x0 0x400>;
210 #size-cells = <0>;
211 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
217 reg = <0x0 0x2110000 0x0 0x400>;
222 #size-cells = <0>;
229 reg = <0x0 0x2120000 0x0 0x400>;
234 #size-cells = <0>;
239 reg = <0x0 0x2130000 0x0 0x400>;
244 #size-cells = <0>;
249 reg = <0x0 0x2140000 0x0 0x400>;
254 #size-cells = <0>;
259 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
261 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
266 ti,otap-del-sel-legacy = <0x0>;
267 ti,otap-del-sel-mmc-hs = <0x0>;
268 ti,otap-del-sel-sd-hs = <0x0>;
269 ti,otap-del-sel-sdr12 = <0x0>;
270 ti,otap-del-sel-sdr25 = <0x0>;
271 ti,otap-del-sel-sdr50 = <0x8>;
272 ti,otap-del-sel-sdr104 = <0x7>;
273 ti,otap-del-sel-ddr50 = <0x5>;
274 ti,otap-del-sel-ddr52 = <0x5>;
275 ti,otap-del-sel-hs200 = <0x5>;
276 ti,otap-del-sel-hs400 = <0x0>;
277 ti,trm-icp = <0x8>;
283 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
285 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
288 ti,otap-del-sel-legacy = <0x0>;
289 ti,otap-del-sel-mmc-hs = <0x0>;
290 ti,otap-del-sel-sd-hs = <0x0>;
291 ti,otap-del-sel-sdr12 = <0x0>;
292 ti,otap-del-sel-sdr25 = <0x0>;
293 ti,otap-del-sel-sdr50 = <0x8>;
294 ti,otap-del-sel-sdr104 = <0x7>;
295 ti,otap-del-sel-ddr50 = <0x4>;
296 ti,otap-del-sel-ddr52 = <0x4>;
297 ti,otap-del-sel-hs200 = <0x7>;
298 ti,clkbuf-sel = <0x7>;
299 ti,otap-del-sel = <0x2>;
300 ti,trm-icp = <0x8>;
306 reg = <0 0x00100000 0 0x1c000>;
309 ranges = <0x0 0x0 0x00100000 0x1c000>;
313 reg = <0x00004060 0x4>;
318 reg = <0x00004070 0x4>;
323 reg = <0x00000210 0x4>;
328 reg = <0x00004080 0x4>;
333 reg = <0x00004090 0x4>;
339 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
340 <0x4090 0x3>; /* SERDES1 lane select */
345 reg = <0x0000041e0 0x14>;
350 reg = <0x4140 0x18>;
357 reg = <0x0 0x4000000 0x0 0x4000>;
360 ranges = <0x0 0x0 0x4000000 0x20000>;
371 reg = <0x10000 0x10000>;
388 reg = <0x0 0x4100000 0x0 0x54>;
389 syscon-phy-power = <&scm_conf 0x4000>;
390 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
392 #phy-cells = <0>;
397 reg = <0x0 0x4020000 0x0 0x4000>;
400 ranges = <0x0 0x0 0x4020000 0x20000>;
410 reg = <0x10000 0x10000>;
426 reg = <0x0 0x4110000 0x0 0x54>;
427 syscon-phy-power = <&scm_conf 0x4020>;
428 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
430 #phy-cells = <0>;
435 reg = <0x0 0x00a00000 0x0 0x400>;
442 ti,interrupt-ranges = <0 392 32>;
449 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
457 reg = <0x0 0x310e0000 0x0 0x2000>;
464 ti,interrupt-ranges = <0 64 64>,
470 reg = <0x0 0x33d00000 0x0 0x100000>;
474 #interrupt-cells = <0>;
477 ti,interrupt-ranges = <0 0 256>;
484 reg = <0x00 0x32c00000 0x00 0x100000>,
485 <0x00 0x32400000 0x00 0x100000>,
486 <0x00 0x32800000 0x00 0x100000>;
493 reg = <0x00 0x30e00000 0x00 0x1000>;
499 reg = <0x00 0x31f80000 0x00 0x200>;
508 reg = <0x00 0x31f81000 0x00 0x200>;
517 reg = <0x00 0x31f82000 0x00 0x200>;
526 reg = <0x00 0x31f83000 0x00 0x200>;
535 reg = <0x00 0x31f84000 0x00 0x200>;
544 reg = <0x00 0x31f85000 0x00 0x200>;
553 reg = <0x00 0x31f86000 0x00 0x200>;
562 reg = <0x00 0x31f87000 0x00 0x200>;
571 reg = <0x00 0x31f88000 0x00 0x200>;
580 reg = <0x00 0x31f89000 0x00 0x200>;
589 reg = <0x00 0x31f8a000 0x00 0x200>;
598 reg = <0x00 0x31f8b000 0x00 0x200>;
607 reg = <0x0 0x3c000000 0x0 0x400000>,
608 <0x0 0x38000000 0x0 0x400000>,
609 <0x0 0x31120000 0x0 0x100>,
610 <0x0 0x33000000 0x0 0x40000>;
613 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
621 reg = <0x0 0x31150000 0x0 0x100>,
622 <0x0 0x34000000 0x0 0x100000>,
623 <0x0 0x35000000 0x0 0x100000>;
632 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
633 <0xd>; /* TX_CHAN */
634 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
635 <0xa>; /* RX_CHAN */
636 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
641 reg = <0x0 0x310d0000 0x0 0x400>;
651 #clock-cells = <0>;
664 reg = <0x0 0x600000 0x0 0x100>;
672 ti,davinci-gpio-unbanked = <0>;
673 clocks = <&k3_clks 57 0>;
679 reg = <0x0 0x601000 0x0 0x100>;
687 ti,davinci-gpio-unbanked = <0>;
688 clocks = <&k3_clks 58 0>;
694 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x…
699 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
700 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
703 bus-range = <0x0 0xff>;
708 msi-map = <0x0 &gic_its 0x0 0x10000>;
714 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0…
727 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x…
732 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
733 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
736 bus-range = <0x0 0xff>;
741 msi-map = <0x0 &gic_its 0x10000 0x10000>;
747 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0…
760 reg = <0x0 0x02b00000 0x0 0x2000>,
761 <0x0 0x02b08000 0x0 0x1000>;
767 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
770 clocks = <&k3_clks 104 0>;
777 reg = <0x0 0x02b10000 0x0 0x2000>,
778 <0x0 0x02b18000 0x0 0x1000>;
784 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
787 clocks = <&k3_clks 105 0>;
794 reg = <0x0 0x02b20000 0x0 0x2000>,
795 <0x0 0x02b28000 0x0 0x1000>;
801 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
804 clocks = <&k3_clks 106 0>;
811 reg = <0x0 0x06f03000 0x0 0x400>,
812 <0x0 0x06f03800 0x0 0x40>;
816 ti,camerrx-control = <&scm_conf 0x40c0>;
818 clocks = <&k3_clks 2 0>;
823 #size-cells = <0>;
825 csi2_0: port@0 {
826 reg = <0>;
833 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
834 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
835 <0x0 0x04a06000 0x0 0x1000>, /* vid */
836 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
837 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
838 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
839 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
866 #size-cells = <0>;
873 reg = <0x0 0x3000000 0x0 0x100>;
875 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
882 reg = <0x0 0x3010000 0x0 0x100>;
884 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
891 reg = <0x0 0x3020000 0x0 0x100>;
893 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
900 reg = <0x0 0x3030000 0x0 0x100>;
902 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
909 reg = <0x0 0x3040000 0x0 0x100>;
911 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
918 reg = <0x0 0x3050000 0x0 0x100>;
920 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
926 reg = <0x00 0xb000000 0x00 0x80000>;
930 ranges = <0x0 0x00 0xb000000 0x80000>;
932 icssg0_mem: memories@0 {
933 reg = <0x0 0x2000>,
934 <0x2000 0x2000>,
935 <0x10000 0x10000>;
942 reg = <0x26000 0x200>;
945 ranges = <0x0 0x26000 0x2000>;
949 #size-cells = <0>;
952 reg = <0x3c>;
953 #clock-cells = <0>;
961 reg = <0x30>;
962 #clock-cells = <0>;
973 reg = <0x32000 0x100>;
978 reg = <0x33000 0x1000>;
983 reg = <0x20000 0x2000>;
1002 reg = <0x34000 0x4000>,
1003 <0x22000 0x100>,
1004 <0x22400 0x100>;
1011 reg = <0x4000 0x2000>,
1012 <0x23000 0x100>,
1013 <0x23400 0x100>;
1020 reg = <0xa000 0x1800>,
1021 <0x25000 0x100>,
1022 <0x25400 0x100>;
1029 reg = <0x38000 0x4000>,
1030 <0x24000 0x100>,
1031 <0x24400 0x100>;
1038 reg = <0x6000 0x2000>,
1039 <0x23800 0x100>,
1040 <0x23c00 0x100>;
1047 reg = <0xc000 0x1800>,
1048 <0x25800 0x100>,
1049 <0x25c00 0x100>;
1056 reg = <0x32400 0x100>;
1060 #size-cells = <0>;
1067 reg = <0x00 0xb100000 0x00 0x80000>;
1071 ranges = <0x0 0x00 0xb100000 0x80000>;
1073 icssg1_mem: memories@0 {
1074 reg = <0x0 0x2000>,
1075 <0x2000 0x2000>,
1076 <0x10000 0x10000>;
1083 reg = <0x26000 0x200>;
1086 ranges = <0x0 0x26000 0x2000>;
1090 #size-cells = <0>;
1093 reg = <0x3c>;
1094 #clock-cells = <0>;
1102 reg = <0x30>;
1103 #clock-cells = <0>;
1114 reg = <0x32000 0x100>;
1119 reg = <0x33000 0x1000>;
1124 reg = <0x20000 0x2000>;
1143 reg = <0x34000 0x4000>,
1144 <0x22000 0x100>,
1145 <0x22400 0x100>;
1152 reg = <0x4000 0x2000>,
1153 <0x23000 0x100>,
1154 <0x23400 0x100>;
1161 reg = <0xa000 0x1800>,
1162 <0x25000 0x100>,
1163 <0x25400 0x100>;
1170 reg = <0x38000 0x4000>,
1171 <0x24000 0x100>,
1172 <0x24400 0x100>;
1179 reg = <0x6000 0x2000>,
1180 <0x23800 0x100>,
1181 <0x23c00 0x100>;
1188 reg = <0xc000 0x1800>,
1189 <0x25800 0x100>,
1190 <0x25c00 0x100>;
1197 reg = <0x32400 0x100>;
1201 #size-cells = <0>;
1208 reg = <0x00 0xb200000 0x00 0x80000>;
1212 ranges = <0x0 0x00 0xb200000 0x80000>;
1214 icssg2_mem: memories@0 {
1215 reg = <0x0 0x2000>,
1216 <0x2000 0x2000>,
1217 <0x10000 0x10000>;
1224 reg = <0x26000 0x200>;
1227 ranges = <0x0 0x26000 0x2000>;
1231 #size-cells = <0>;
1234 reg = <0x3c>;
1235 #clock-cells = <0>;
1243 reg = <0x30>;
1244 #clock-cells = <0>;
1255 reg = <0x32000 0x100>;
1260 reg = <0x33000 0x1000>;
1265 reg = <0x20000 0x2000>;
1284 reg = <0x34000 0x4000>,
1285 <0x22000 0x100>,
1286 <0x22400 0x100>;
1293 reg = <0x4000 0x2000>,
1294 <0x23000 0x100>,
1295 <0x23400 0x100>;
1302 reg = <0xa000 0x1800>,
1303 <0x25000 0x100>,
1304 <0x25400 0x100>;
1311 reg = <0x38000 0x4000>,
1312 <0x24000 0x100>,
1313 <0x24400 0x100>;
1320 reg = <0x6000 0x2000>,
1321 <0x23800 0x100>,
1322 <0x23c00 0x100>;
1329 reg = <0xc000 0x1800>,
1330 <0x25800 0x100>,
1331 <0x25c00 0x100>;
1338 reg = <0x32400 0x100>;
1342 #size-cells = <0>;