Lines Matching +full:tchsh +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/mux/ti-serdes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-am642.dtsi"
16 compatible = "ti,am642-evm", "ti,am642";
20 stdout-path = "serial2:115200n8";
31 reserved-memory {
32 #address-cells = <2>;
33 #size-cells = <2>;
37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
39 no-map;
42 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
43 compatible = "shared-dma-pool";
45 no-map;
48 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
49 compatible = "shared-dma-pool";
51 no-map;
54 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
55 compatible = "shared-dma-pool";
57 no-map;
60 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
61 compatible = "shared-dma-pool";
63 no-map;
66 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
67 compatible = "shared-dma-pool";
69 no-map;
72 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
73 compatible = "shared-dma-pool";
75 no-map;
78 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
79 compatible = "shared-dma-pool";
81 no-map;
84 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
85 compatible = "shared-dma-pool";
87 no-map;
90 rtos_ipc_memory_region: ipc-memories@a5000000 {
93 no-map;
97 evm_12v0: fixedregulator-evm12v0 {
99 compatible = "regulator-fixed";
100 regulator-name = "evm_12v0";
101 regulator-min-microvolt = <12000000>;
102 regulator-max-microvolt = <12000000>;
103 regulator-always-on;
104 regulator-boot-on;
107 vsys_5v0: fixedregulator-vsys5v0 {
109 compatible = "regulator-fixed";
110 regulator-name = "vsys_5v0";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 vin-supply = <&evm_12v0>;
114 regulator-always-on;
115 regulator-boot-on;
118 vsys_3v3: fixedregulator-vsys3v3 {
120 compatible = "regulator-fixed";
121 regulator-name = "vsys_3v3";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 vin-supply = <&evm_12v0>;
125 regulator-always-on;
126 regulator-boot-on;
129 vdd_mmc1: fixed-regulator-sd {
131 compatible = "regulator-fixed";
132 regulator-name = "vdd_mmc1";
133 regulator-min-microvolt = <3300000>;
134 regulator-max-microvolt = <3300000>;
135 regulator-boot-on;
136 enable-active-high;
137 vin-supply = <&vsys_3v3>;
141 vddb: fixedregulator-vddb {
142 compatible = "regulator-fixed";
143 regulator-name = "vddb_3v3_display";
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 vin-supply = <&vsys_3v3>;
147 regulator-always-on;
148 regulator-boot-on;
152 compatible = "gpio-leds";
154 led-0 {
155 label = "am64-evm:red:heartbeat";
157 linux,default-trigger = "heartbeat";
159 default-state = "off";
163 mdio_mux: mux-controller {
164 compatible = "gpio-mux";
165 #mux-control-cells = <0>;
167 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
170 mdio-mux-1 {
171 compatible = "mdio-mux-multiplexer";
172 mux-controls = <&mdio_mux>;
173 mdio-parent-bus = <&cpsw3g_mdio>;
174 #address-cells = <1>;
175 #size-cells = <0>;
179 #address-cells = <1>;
180 #size-cells = <0>;
182 cpsw3g_phy3: ethernet-phy@3 {
188 transceiver1: can-phy0 {
190 #phy-cells = <0>;
191 max-bitrate = <5000000>;
192 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
195 transceiver2: can-phy1 {
197 #phy-cells = <0>;
198 max-bitrate = <5000000>;
199 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
204 main_mmc1_pins_default: main-mmc1-pins-default {
205 pinctrl-single,pins = <
218 main_uart0_pins_default: main-uart0-pins-default {
219 pinctrl-single,pins = <
227 main_spi0_pins_default: main-spi0-pins-default {
228 pinctrl-single,pins = <
236 main_i2c1_pins_default: main-i2c1-pins-default {
237 pinctrl-single,pins = <
243 mdio1_pins_default: mdio1-pins-default {
244 pinctrl-single,pins = <
250 rgmii1_pins_default: rgmii1-pins-default {
251 pinctrl-single,pins = <
267 rgmii2_pins_default: rgmii2-pins-default {
268 pinctrl-single,pins = <
284 main_usb0_pins_default: main-usb0-pins-default {
285 pinctrl-single,pins = <
290 ospi0_pins_default: ospi0-pins-default {
291 pinctrl-single,pins = <
306 main_ecap0_pins_default: main-ecap0-pins-default {
307 pinctrl-single,pins = <
312 main_mcan0_pins_default: main-mcan0-pins-default {
313 pinctrl-single,pins = <
319 main_mcan1_pins_default: main-mcan1-pins-default {
320 pinctrl-single,pins = <
328 pinctrl-names = "default";
329 pinctrl-0 = <&main_uart0_pins_default>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&main_i2c1_pins_default>;
368 clock-frequency = <400000>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
387 /* osd9616p0899-10 */
389 compatible = "solomon,ssd1306fb-i2c";
391 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
392 vbat-supply = <&vddb>;
395 solomon,com-seq;
396 solomon,com-invdir;
397 solomon,page-offset = <0>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&main_spi0_pins_default>;
427 ti,pindir-d0-out-d1-in;
431 spi-max-frequency = <1000000>;
432 spi-cs-high;
433 data-size = <16>;
439 bus-width = <8>;
440 non-removable;
441 ti,driver-strength-ohm = <50>;
442 disable-wp;
447 vmmc-supply = <&vdd_mmc1>;
448 pinctrl-names = "default";
449 bus-width = <4>;
450 pinctrl-0 = <&main_mmc1_pins_default>;
451 ti,driver-strength-ohm = <50>;
452 disable-wp;
456 ti,vbus-divider;
457 ti,usb2-only;
462 maximum-speed = "high-speed";
463 pinctrl-names = "default";
464 pinctrl-0 = <&main_usb0_pins_default>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&mdio1_pins_default
475 phy-mode = "rgmii-rxid";
476 phy-handle = <&cpsw3g_phy0>;
480 phy-mode = "rgmii-rxid";
481 phy-handle = <&cpsw3g_phy3>;
485 cpsw3g_phy0: ethernet-phy@0 {
487 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
488 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&ospi0_pins_default>;
502 compatible = "jedec,spi-nor";
504 spi-tx-bus-width = <8>;
505 spi-rx-bus-width = <8>;
506 spi-max-frequency = <25000000>;
507 cdns,tshsl-ns = <60>;
508 cdns,tsd2d-ns = <60>;
509 cdns,tchsh-ns = <60>;
510 cdns,tslch-ns = <60>;
511 cdns,read-delay = <4>;
516 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
517 ti,mbox-rx = <0 0 2>;
518 ti,mbox-tx = <1 0 2>;
521 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
522 ti,mbox-rx = <2 0 2>;
523 ti,mbox-tx = <3 0 2>;
532 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
533 ti,mbox-rx = <0 0 2>;
534 ti,mbox-tx = <1 0 2>;
537 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
538 ti,mbox-rx = <2 0 2>;
539 ti,mbox-tx = <3 0 2>;
548 mbox_m4_0: mbox-m4-0 {
549 ti,mbox-rx = <0 0 2>;
550 ti,mbox-tx = <1 0 2>;
560 memory-region = <&main_r5fss0_core0_dma_memory_region>,
566 memory-region = <&main_r5fss0_core1_dma_memory_region>,
572 memory-region = <&main_r5fss1_core0_dma_memory_region>,
578 memory-region = <&main_r5fss1_core1_dma_memory_region>,
583 idle-states = <AM64_SERDES0_LANE0_PCIE0>;
589 cdns,num-lanes = <1>;
590 #phy-cells = <0>;
591 cdns,phy-type = <PHY_TYPE_PCIE>;
597 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
599 phy-names = "pcie-phy";
600 num-lanes = <1>;
605 phy-names = "pcie-phy";
606 num-lanes = <1>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&main_ecap0_pins_default>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&main_mcan0_pins_default>;
675 pinctrl-names = "default";
676 pinctrl-0 = <&main_mcan1_pins_default>;