Lines Matching +full:0 +full:x0d000000
13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
42 reg = <0x0 0x43000000 0x0 0x20000>;
45 ranges = <0x0 0x0 0x43000000 0x20000>;
50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
61 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
62 <0x00 0x01840000 0x00 0xC0000>, /* GICR */
63 <0x01 0x00000000 0x00 0x2000>, /* GICC */
64 <0x01 0x00010000 0x00 0x1000>, /* GICH */
65 <0x01 0x00020000 0x00 0x2000>; /* GICV */
74 reg = <0x00 0x01820000 0x00 0x10000>;
75 socionext,synquacer-pre-its = <0x1000000 0x400000>;
86 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
94 reg = <0x00 0x4d000000 0x00 0x80000>,
95 <0x00 0x4a600000 0x00 0x80000>,
96 <0x00 0x4a400000 0x00 0x80000>;
103 reg = <0x00 0x48000000 0x00 0x100000>;
104 #interrupt-cells = <0>;
116 reg = <0x00 0x485c0100 0x00 0x100>,
117 <0x00 0x4c000000 0x00 0x20000>,
118 <0x00 0x4a820000 0x00 0x20000>,
119 <0x00 0x4aa40000 0x00 0x20000>,
120 <0x00 0x4bc00000 0x00 0x100000>;
127 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
128 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
129 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
134 reg = <0x00 0x485c0000 0x00 0x100>,
135 <0x00 0x4a800000 0x00 0x20000>,
136 <0x00 0x4aa00000 0x00 0x40000>,
137 <0x00 0x4b800000 0x00 0x400000>;
144 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
145 <0x24>, /* CPSW_TX_CHAN */
146 <0x25>, /* SAUL_TX_0_CHAN */
147 <0x26>, /* SAUL_TX_1_CHAN */
148 <0x27>, /* ICSSG_0_TX_CHAN */
149 <0x28>; /* ICSSG_1_TX_CHAN */
150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
151 <0x11>, /* RING_CPSW_TX_CHAN */
152 <0x12>, /* RING_SAUL_TX_0_CHAN */
153 <0x13>, /* RING_SAUL_TX_1_CHAN */
154 <0x14>, /* RING_ICSSG_0_TX_CHAN */
155 <0x15>; /* RING_ICSSG_1_TX_CHAN */
156 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
157 <0x2b>, /* CPSW_RX_CHAN */
158 <0x2d>, /* SAUL_RX_0_CHAN */
159 <0x2f>, /* SAUL_RX_1_CHAN */
160 <0x31>, /* SAUL_RX_2_CHAN */
161 <0x33>, /* SAUL_RX_3_CHAN */
162 <0x35>, /* ICSSG_0_RX_CHAN */
163 <0x37>; /* ICSSG_1_RX_CHAN */
164 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
165 <0x2c>, /* FLOW_CPSW_RX_CHAN */
166 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
167 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
168 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
169 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
180 reg = <0x00 0x44043000 0x00 0xfe0>;
200 reg = <0x00 0xf4000 0x00 0x2d0>;
203 pinctrl-single,function-mask = <0xffffffff>;
208 reg = <0x00 0x43000000 0x00 0x20000>;
211 ranges = <0x00 0x00 0x43000000 0x20000>;
215 reg = <0x00000014 0x4>;
220 reg = <0x4044 0x8>;
226 reg = <0x4130 0x4>;
233 reg = <0x00 0x02800000 0x00 0x100>;
238 clocks = <&k3_clks 146 0>;
244 reg = <0x00 0x02810000 0x00 0x100>;
249 clocks = <&k3_clks 152 0>;
255 reg = <0x00 0x02820000 0x00 0x100>;
260 clocks = <&k3_clks 153 0>;
266 reg = <0x00 0x02830000 0x00 0x100>;
271 clocks = <&k3_clks 154 0>;
277 reg = <0x00 0x02840000 0x00 0x100>;
282 clocks = <&k3_clks 155 0>;
288 reg = <0x00 0x02850000 0x00 0x100>;
293 clocks = <&k3_clks 156 0>;
299 reg = <0x00 0x02860000 0x00 0x100>;
304 clocks = <&k3_clks 158 0>;
310 reg = <0x00 0x20000000 0x00 0x100>;
313 #size-cells = <0>;
321 reg = <0x00 0x20010000 0x00 0x100>;
324 #size-cells = <0>;
332 reg = <0x00 0x20020000 0x00 0x100>;
335 #size-cells = <0>;
343 reg = <0x00 0x20030000 0x00 0x100>;
346 #size-cells = <0>;
354 reg = <0x00 0x20100000 0x00 0x400>;
357 #size-cells = <0>;
359 clocks = <&k3_clks 141 0>;
360 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
366 reg = <0x00 0x20110000 0x00 0x400>;
369 #size-cells = <0>;
371 clocks = <&k3_clks 142 0>;
376 reg = <0x00 0x20120000 0x00 0x400>;
379 #size-cells = <0>;
381 clocks = <&k3_clks 143 0>;
386 reg = <0x00 0x20130000 0x00 0x400>;
389 #size-cells = <0>;
391 clocks = <&k3_clks 144 0>;
396 reg = <0x00 0x20140000 0x00 0x400>;
399 #size-cells = <0>;
401 clocks = <&k3_clks 145 0>;
406 reg = <0x00 0x00a00000 0x00 0x800>;
413 ti,interrupt-ranges = <0 32 16>;
418 reg = <0x0 0x00600000 0x0 0x100>;
427 ti,davinci-gpio-unbanked = <0>;
429 clocks = <&k3_clks 77 0>;
435 reg = <0x0 0x00601000 0x0 0x100>;
444 ti,davinci-gpio-unbanked = <0>;
446 clocks = <&k3_clks 78 0>;
452 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
455 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
459 ti,trm-icp = <0x2>;
460 ti,otap-del-sel-legacy = <0x0>;
461 ti,otap-del-sel-mmc-hs = <0x0>;
462 ti,otap-del-sel-ddr52 = <0x6>;
463 ti,otap-del-sel-hs200 = <0x7>;
468 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
473 ti,trm-icp = <0x2>;
474 ti,otap-del-sel-legacy = <0x0>;
475 ti,otap-del-sel-sd-hs = <0xf>;
476 ti,otap-del-sel-sdr12 = <0xf>;
477 ti,otap-del-sel-sdr25 = <0xf>;
478 ti,otap-del-sel-sdr50 = <0xc>;
479 ti,otap-del-sel-sdr104 = <0x6>;
480 ti,otap-del-sel-ddr50 = <0x9>;
481 ti,clkbuf-sel = <0x7>;
488 reg = <0x0 0x8000000 0x0 0x200000>;
490 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
491 clocks = <&k3_clks 13 0>;
497 dmas = <&main_pktdma 0xC500 15>,
498 <&main_pktdma 0xC501 15>,
499 <&main_pktdma 0xC502 15>,
500 <&main_pktdma 0xC503 15>,
501 <&main_pktdma 0xC504 15>,
502 <&main_pktdma 0xC505 15>,
503 <&main_pktdma 0xC506 15>,
504 <&main_pktdma 0xC507 15>,
505 <&main_pktdma 0x4500 15>;
511 #size-cells = <0>;
519 ti,syscon-efuse = <&main_conf 0x200>;
533 reg = <0x0 0xf00 0x0 0x100>;
535 #size-cells = <0>;
536 clocks = <&k3_clks 13 0>;
543 reg = <0x0 0x3d000 0x0 0x400>;
555 reg = <0x0 0x39000000 0x0 0x400>;
558 clocks = <&k3_clks 84 0>;
560 assigned-clocks = <&k3_clks 84 0>;
570 reg = <0x0 0xa40000 0x0 0x800>;
573 pinctrl-single,function-mask = <0x000107ff>;
578 reg = <0x00 0xf900000 0x00 0x100>;
589 reg = <0x00 0xf400000 0x00 0x10000>,
590 <0x00 0xf410000 0x00 0x10000>,
591 <0x00 0xf420000 0x00 0x10000>;
595 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
608 reg = <0x00 0x28001000 0x00 0x1000>;
610 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
611 clocks = <&k3_clks 0 0>;
612 assigned-clocks = <&k3_clks 0 0>;
613 assigned-clock-parents = <&k3_clks 0 3>;
625 reg = <0x00 0x0fc00000 0x00 0x70000>;
632 reg = <0x00 0x0fc40000 0x00 0x100>,
633 <0x05 0x00000000 0x01 0x00000000>;
637 cdns,trigger-address = <0x0>;
638 #address-cells = <0x1>;
639 #size-cells = <0x0>;
650 reg = <0x00 0x2a000000 0x00 0x1000>;
656 reg = <0x00 0x29020000 0x00 0x200>;
666 reg = <0x00 0x29030000 0x00 0x200>;
676 reg = <0x00 0x29040000 0x00 0x200>;
686 reg = <0x00 0x29050000 0x00 0x200>;
696 reg = <0x00 0x29060000 0x00 0x200>;
705 reg = <0x00 0x29070000 0x00 0x200>;
714 ti,cluster-mode = <0>;
717 ranges = <0x78000000 0x00 0x78000000 0x10000>,
718 <0x78100000 0x00 0x78100000 0x10000>,
719 <0x78200000 0x00 0x78200000 0x08000>,
720 <0x78300000 0x00 0x78300000 0x08000>;
725 reg = <0x78000000 0x00010000>,
726 <0x78100000 0x00010000>;
730 ti,sci-proc-ids = <0x01 0xff>;
740 reg = <0x78200000 0x00008000>,
741 <0x78300000 0x00008000>;
745 ti,sci-proc-ids = <0x02 0xff>;
756 ti,cluster-mode = <0>;
759 ranges = <0x78400000 0x00 0x78400000 0x10000>,
760 <0x78500000 0x00 0x78500000 0x10000>,
761 <0x78600000 0x00 0x78600000 0x08000>,
762 <0x78700000 0x00 0x78700000 0x08000>;
767 reg = <0x78400000 0x00010000>,
768 <0x78500000 0x00010000>;
772 ti,sci-proc-ids = <0x06 0xff>;
782 reg = <0x78600000 0x00008000>,
783 <0x78700000 0x00008000>;
787 ti,sci-proc-ids = <0x07 0xff>;
801 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
806 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
813 reg = <0x0f000000 0x00010000>;
815 resets = <&serdes_wiz0 0>;
827 #size-cells = <0>;
834 reg = <0x00 0x0f102000 0x00 0x1000>,
835 <0x00 0x0f100000 0x00 0x400>,
836 <0x00 0x0d000000 0x00 0x00800000>,
837 <0x00 0x68000000 0x00 0x00001000>;
842 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
846 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
850 bus-range = <0x0 0xff>;
852 vendor-id = <0x104c>;
853 device-id = <0xb010>;
854 msi-map = <0x0 &gic_its 0x0 0x10000>;
855 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
856 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
857 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
862 reg = <0x00 0x0f102000 0x00 0x1000>,
863 <0x00 0x0f100000 0x00 0x400>,
864 <0x00 0x0d000000 0x00 0x00800000>,
865 <0x00 0x68000000 0x00 0x08000000>;
869 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
873 clocks = <&k3_clks 114 0>;
881 reg = <0x0 0x23000000 0x0 0x100>;
883 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
890 reg = <0x0 0x23010000 0x0 0x100>;
892 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
899 reg = <0x0 0x23020000 0x0 0x100>;
901 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
908 reg = <0x0 0x23030000 0x0 0x100>;
910 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
917 reg = <0x0 0x23040000 0x0 0x100>;
919 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
926 reg = <0x0 0x23050000 0x0 0x100>;
928 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
935 reg = <0x0 0x23060000 0x0 0x100>;
937 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
944 reg = <0x0 0x23070000 0x0 0x100>;
946 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
953 reg = <0x0 0x23080000 0x0 0x100>;
955 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
962 reg = <0x0 0x23100000 0x0 0x60>;
964 clocks = <&k3_clks 51 0>;
971 reg = <0x0 0x23110000 0x0 0x60>;
973 clocks = <&k3_clks 52 0>;
980 reg = <0x0 0x23120000 0x0 0x60>;
982 clocks = <&k3_clks 53 0>;
988 reg = <0x00 0xe000000 0x00 0x100>;
989 clocks = <&k3_clks 125 0>;
991 assigned-clocks = <&k3_clks 125 0>;
997 reg = <0x00 0xe010000 0x00 0x100>;
998 clocks = <&k3_clks 126 0>;
1000 assigned-clocks = <&k3_clks 126 0>;
1006 reg = <0x00 0x30000000 0x00 0x80000>;
1010 ranges = <0x0 0x00 0x30000000 0x80000>;
1012 icssg0_mem: memories@0 {
1013 reg = <0x0 0x2000>,
1014 <0x2000 0x2000>,
1015 <0x10000 0x10000>;
1021 reg = <0x26000 0x200>;
1024 ranges = <0x0 0x26000 0x2000>;
1028 #size-cells = <0>;
1031 reg = <0x3c>;
1032 #clock-cells = <0>;
1033 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
1040 reg = <0x30>;
1041 #clock-cells = <0>;
1052 reg = <0x32000 0x100>;
1057 reg = <0x33000 0x1000>;
1062 reg = <0x20000 0x2000>;
1081 reg = <0x34000 0x3000>,
1082 <0x22000 0x100>,
1083 <0x22400 0x100>;
1090 reg = <0x4000 0x2000>,
1091 <0x23000 0x100>,
1092 <0x23400 0x100>;
1099 reg = <0xa000 0x1800>,
1100 <0x25000 0x100>,
1101 <0x25400 0x100>;
1108 reg = <0x38000 0x3000>,
1109 <0x24000 0x100>,
1110 <0x24400 0x100>;
1117 reg = <0x6000 0x2000>,
1118 <0x23800 0x100>,
1119 <0x23c00 0x100>;
1126 reg = <0xc000 0x1800>,
1127 <0x25800 0x100>,
1128 <0x25c00 0x100>;
1135 reg = <0x32400 0x100>;
1139 #size-cells = <0>;
1146 reg = <0x00 0x30080000 0x00 0x80000>;
1150 ranges = <0x0 0x00 0x30080000 0x80000>;
1152 icssg1_mem: memories@0 {
1153 reg = <0x0 0x2000>,
1154 <0x2000 0x2000>,
1155 <0x10000 0x10000>;
1161 reg = <0x26000 0x200>;
1164 ranges = <0x0 0x26000 0x2000>;
1168 #size-cells = <0>;
1171 reg = <0x3c>;
1172 #clock-cells = <0>;
1173 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
1180 reg = <0x30>;
1181 #clock-cells = <0>;
1192 reg = <0x32000 0x100>;
1197 reg = <0x33000 0x1000>;
1202 reg = <0x20000 0x2000>;
1221 reg = <0x34000 0x4000>,
1222 <0x22000 0x100>,
1223 <0x22400 0x100>;
1230 reg = <0x4000 0x2000>,
1231 <0x23000 0x100>,
1232 <0x23400 0x100>;
1239 reg = <0xa000 0x1800>,
1240 <0x25000 0x100>,
1241 <0x25400 0x100>;
1248 reg = <0x38000 0x4000>,
1249 <0x24000 0x100>,
1250 <0x24400 0x100>;
1257 reg = <0x6000 0x2000>,
1258 <0x23800 0x100>,
1259 <0x23c00 0x100>;
1266 reg = <0xc000 0x1800>,
1267 <0x25800 0x100>,
1268 <0x25c00 0x100>;
1275 reg = <0x32400 0x100>;
1277 #size-cells = <0>;
1278 clocks = <&k3_clks 82 0>;
1286 reg = <0x00 0x20701000 0x00 0x200>,
1287 <0x00 0x20708000 0x00 0x8000>;
1290 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
1295 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1300 reg = <0x00 0x20711000 0x00 0x200>,
1301 <0x00 0x20718000 0x00 0x8000>;
1304 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
1309 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1314 reg = <0x00 0x40900000 0x00 0x1200>;
1318 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
1319 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
1320 <&main_pktdma 0x4003 0>;
1325 reg = <0x00 0x40910000 0x00 0x7d>;
1335 clocks = <&k3_clks 80 0>;
1337 reg = <0x00 0x03b000000 0x00 0x400>,
1338 <0x00 0x050000000 0x00 0x8000000>;
1353 reg = <0x00 0x25010000 0x00 0x2000>;
1356 clocks = <&k3_clks 54 0>;