Lines Matching +full:k2g +full:- +full:sci +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
23 interrupt-controller;
36 gic_its: msi-controller@1820000 {
37 compatible = "arm,gic-v3-its";
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
40 msi-controller;
41 #msi-cells = <1>;
46 compatible = "syscon", "simple-mfd";
48 #address-cells = <1>;
49 #size-cells = <1>;
53 compatible = "ti,am654-phy-gmii-sel";
55 #phy-cells = <1>;
59 compatible = "ti,am62-epwm-tbclk", "syscon";
61 #clock-cells = <1>;
66 compatible = "simple-mfd";
67 #address-cells = <2>;
68 #size-cells = <2>;
69 dma-ranges;
72 ti,sci-dev-id = <25>;
75 compatible = "ti,am654-secure-proxy";
76 #mbox-cells = <1>;
77 reg-names = "target_data", "rt", "scfg";
81 interrupt-names = "rx_012";
85 inta_main_dmss: interrupt-controller@48000000 {
86 compatible = "ti,sci-inta";
88 #interrupt-cells = <0>;
89 interrupt-controller;
90 interrupt-parent = <&gic500>;
91 msi-controller;
92 ti,sci = <&dmsc>;
93 ti,sci-dev-id = <28>;
94 ti,interrupt-ranges = <4 68 36>;
95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
98 main_bcdma: dma-controller@485c0100 {
99 compatible = "ti,am64-dmss-bcdma";
105 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
106 msi-parent = <&inta_main_dmss>;
107 #dma-cells = <3>;
109 ti,sci = <&dmsc>;
110 ti,sci-dev-id = <26>;
111 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
112 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
113 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
116 main_pktdma: dma-controller@485c0000 {
117 compatible = "ti,am64-dmss-pktdma";
122 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
123 msi-parent = <&inta_main_dmss>;
124 #dma-cells = <2>;
126 ti,sci = <&dmsc>;
127 ti,sci-dev-id = <30>;
128 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
132 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
136 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
142 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
149 dmsc: system-controller@44043000 {
150 compatible = "ti,k2g-sci";
151 ti,host-id = <12>;
152 mbox-names = "rx", "tx";
155 reg-names = "debug_messages";
158 k3_pds: power-controller {
159 compatible = "ti,sci-pm-domain";
160 #power-domain-cells = <2>;
163 k3_clks: clock-controller {
164 compatible = "ti,k2g-sci-clk";
165 #clock-cells = <2>;
168 k3_reset: reset-controller {
169 compatible = "ti,sci-reset";
170 #reset-cells = <2>;
175 compatible = "ti,am62-sa3ul";
177 power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>;
178 #address-cells = <2>;
179 #size-cells = <2>;
184 dma-names = "tx", "rx1", "rx2";
188 compatible = "pinctrl-single";
190 #pinctrl-cells = <1>;
191 pinctrl-single,register-width = <32>;
192 pinctrl-single,function-mask = <0xffffffff>;
196 compatible = "ti,am64-uart", "ti,am654-uart";
199 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
201 clock-names = "fclk";
205 compatible = "ti,am64-uart", "ti,am654-uart";
208 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
210 clock-names = "fclk";
214 compatible = "ti,am64-uart", "ti,am654-uart";
217 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
219 clock-names = "fclk";
223 compatible = "ti,am64-uart", "ti,am654-uart";
226 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
228 clock-names = "fclk";
232 compatible = "ti,am64-uart", "ti,am654-uart";
235 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
237 clock-names = "fclk";
241 compatible = "ti,am64-uart", "ti,am654-uart";
244 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
246 clock-names = "fclk";
250 compatible = "ti,am64-uart", "ti,am654-uart";
253 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
255 clock-names = "fclk";
259 compatible = "ti,am64-i2c", "ti,omap4-i2c";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
266 clock-names = "fck";
270 compatible = "ti,am64-i2c", "ti,omap4-i2c";
273 #address-cells = <1>;
274 #size-cells = <0>;
275 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
277 clock-names = "fck";
281 compatible = "ti,am64-i2c", "ti,omap4-i2c";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
288 clock-names = "fck";
292 compatible = "ti,am64-i2c", "ti,omap4-i2c";
295 #address-cells = <1>;
296 #size-cells = <0>;
297 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
299 clock-names = "fck";
303 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
306 #address-cells = <1>;
307 #size-cells = <0>;
308 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
313 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
323 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
332 main_gpio_intr: interrupt-controller@a00000 {
333 compatible = "ti,sci-intr";
335 ti,intr-trigger-type = <1>;
336 interrupt-controller;
337 interrupt-parent = <&gic500>;
338 #interrupt-cells = <1>;
339 ti,sci = <&dmsc>;
340 ti,sci-dev-id = <3>;
341 ti,interrupt-ranges = <0 32 16>;
345 compatible = "ti,am64-gpio", "ti,keystone-gpio";
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-parent = <&main_gpio_intr>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
355 ti,davinci-gpio-unbanked = <0>;
356 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
358 clock-names = "gpio";
362 compatible = "ti,am64-gpio", "ti,keystone-gpio";
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-parent = <&main_gpio_intr>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
372 ti,davinci-gpio-unbanked = <0>;
373 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
375 clock-names = "gpio";
379 compatible = "ti,am62-sdhci";
382 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
384 clock-names = "clk_ahb", "clk_xin";
385 assigned-clocks = <&k3_clks 57 6>;
386 assigned-clock-parents = <&k3_clks 57 8>;
387 mmc-ddr-1_8v;
388 mmc-hs200-1_8v;
389 ti,trm-icp = <0x2>;
390 bus-width = <8>;
391 ti,clkbuf-sel = <0x7>;
392 ti,otap-del-sel-legacy = <0x0>;
393 ti,otap-del-sel-mmc-hs = <0x0>;
394 ti,otap-del-sel-ddr52 = <0x9>;
395 ti,otap-del-sel-hs200 = <0x6>;
399 compatible = "ti,am62-sdhci";
402 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
404 clock-names = "clk_ahb", "clk_xin";
405 ti,trm-icp = <0x2>;
406 ti,otap-del-sel-legacy = <0x0>;
407 ti,otap-del-sel-sd-hs = <0x0>;
408 ti,otap-del-sel-sdr12 = <0xf>;
409 ti,otap-del-sel-sdr25 = <0xf>;
410 ti,otap-del-sel-sdr50 = <0xc>;
411 ti,otap-del-sel-sdr104 = <0x6>;
412 ti,otap-del-sel-ddr50 = <0x9>;
413 ti,itap-del-sel-legacy = <0x0>;
414 ti,itap-del-sel-sd-hs = <0x0>;
415 ti,itap-del-sel-sdr12 = <0x0>;
416 ti,itap-del-sel-sdr25 = <0x0>;
417 ti,clkbuf-sel = <0x7>;
418 bus-width = <4>;
422 compatible = "ti,am62-sdhci";
425 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
427 clock-names = "clk_ahb", "clk_xin";
428 ti,trm-icp = <0x2>;
429 ti,otap-del-sel-legacy = <0x0>;
430 ti,otap-del-sel-sd-hs = <0x0>;
431 ti,otap-del-sel-sdr12 = <0xf>;
432 ti,otap-del-sel-sdr25 = <0xf>;
433 ti,otap-del-sel-sdr50 = <0xc>;
434 ti,otap-del-sel-sdr104 = <0x6>;
435 ti,otap-del-sel-ddr50 = <0x9>;
436 ti,itap-del-sel-legacy = <0x0>;
437 ti,itap-del-sel-sd-hs = <0x0>;
438 ti,itap-del-sel-sdr12 = <0x0>;
439 ti,itap-del-sel-sdr25 = <0x0>;
440 ti,clkbuf-sel = <0x7>;
444 compatible = "simple-bus";
446 #address-cells = <2>;
447 #size-cells = <2>;
451 compatible = "ti,am654-ospi", "cdns,qspi-nor";
455 cdns,fifo-depth = <256>;
456 cdns,fifo-width = <4>;
457 cdns,trigger-address = <0x0>;
459 assigned-clocks = <&k3_clks 75 7>;
460 assigned-clock-parents = <&k3_clks 75 8>;
461 assigned-clock-rates = <166666666>;
462 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
463 #address-cells = <1>;
464 #size-cells = <0>;
469 compatible = "ti,am642-cpsw-nuss";
470 #address-cells = <2>;
471 #size-cells = <2>;
473 reg-names = "cpsw_nuss";
476 assigned-clocks = <&k3_clks 13 3>;
477 assigned-clock-parents = <&k3_clks 13 11>;
478 clock-names = "fck";
479 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
490 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
493 ethernet-ports {
494 #address-cells = <1>;
495 #size-cells = <0>;
499 ti,mac-only;
502 mac-address = [00 00 00 00 00 00];
503 ti,syscon-efuse = <&wkup_conf 0x200>;
508 ti,mac-only;
511 mac-address = [00 00 00 00 00 00];
516 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
518 #address-cells = <1>;
519 #size-cells = <0>;
521 clock-names = "fck";
526 compatible = "ti,j721e-cpts";
529 clock-names = "cpts";
530 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
531 interrupt-names = "cpts";
532 ti,cpts-ext-ts-inputs = <4>;
533 ti,cpts-periodic-outputs = <2>;
538 compatible = "ti,am64-hwspinlock";
540 #hwlock-cells = <1>;
544 compatible = "ti,am64-mailbox";
548 #mbox-cells = <1>;
549 ti,mbox-num-users = <4>;
550 ti,mbox-num-fifos = <16>;
554 compatible = "ti,am3352-ecap";
555 #pwm-cells = <3>;
557 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
559 clock-names = "fck";
563 compatible = "ti,am3352-ecap";
564 #pwm-cells = <3>;
566 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
568 clock-names = "fck";
572 compatible = "ti,am3352-ecap";
573 #pwm-cells = <3>;
575 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
577 clock-names = "fck";
584 reg-names = "m_can", "message_ram";
585 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
587 clock-names = "hclk", "cclk";
590 interrupt-names = "int0", "int1";
591 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
595 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
596 #pwm-cells = <3>;
598 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
600 clock-names = "tbclk", "fck";
604 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
605 #pwm-cells = <3>;
607 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
609 clock-names = "tbclk", "fck";
613 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
614 #pwm-cells = <3>;
616 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
618 clock-names = "tbclk", "fck";