Lines Matching +full:0 +full:x4a820000
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
47 reg = <0x00 0x00100000 0x00 0x20000>;
50 ranges = <0x0 0x00 0x00100000 0x20000>;
54 reg = <0x4044 0x8>;
60 reg = <0x4130 0x4>;
70 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
78 reg = <0x00 0x4d000000 0x00 0x80000>,
79 <0x00 0x4a600000 0x00 0x80000>,
80 <0x00 0x4a400000 0x00 0x80000>;
87 reg = <0x00 0x48000000 0x00 0x100000>;
88 #interrupt-cells = <0>;
100 reg = <0x00 0x485c0100 0x00 0x100>,
101 <0x00 0x4c000000 0x00 0x20000>,
102 <0x00 0x4a820000 0x00 0x20000>,
103 <0x00 0x4aa40000 0x00 0x20000>,
104 <0x00 0x4bc00000 0x00 0x100000>;
111 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
112 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
113 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
118 reg = <0x00 0x485c0000 0x00 0x100>,
119 <0x00 0x4a800000 0x00 0x20000>,
120 <0x00 0x4aa00000 0x00 0x40000>,
121 <0x00 0x4b800000 0x00 0x400000>;
128 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
129 <0x24>, /* CPSW_TX_CHAN */
130 <0x25>, /* SAUL_TX_0_CHAN */
131 <0x26>; /* SAUL_TX_1_CHAN */
132 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
133 <0x11>, /* RING_CPSW_TX_CHAN */
134 <0x12>, /* RING_SAUL_TX_0_CHAN */
135 <0x13>; /* RING_SAUL_TX_1_CHAN */
136 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
137 <0x2b>, /* CPSW_RX_CHAN */
138 <0x2d>, /* SAUL_RX_0_CHAN */
139 <0x2f>, /* SAUL_RX_1_CHAN */
140 <0x31>, /* SAUL_RX_2_CHAN */
141 <0x33>; /* SAUL_RX_3_CHAN */
142 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
143 <0x2c>, /* FLOW_CPSW_RX_CHAN */
144 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
145 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
156 reg = <0x00 0x44043000 0x00 0xfe0>;
176 reg = <0x00 0x40900000 0x00 0x1200>;
180 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
182 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
183 <&main_pktdma 0x7507 0>;
189 reg = <0x00 0xf4000 0x00 0x2ac>;
192 pinctrl-single,function-mask = <0xffffffff>;
197 reg = <0x00 0x02800000 0x00 0x100>;
200 clocks = <&k3_clks 146 0>;
206 reg = <0x00 0x02810000 0x00 0x100>;
209 clocks = <&k3_clks 152 0>;
215 reg = <0x00 0x02820000 0x00 0x100>;
218 clocks = <&k3_clks 153 0>;
224 reg = <0x00 0x02830000 0x00 0x100>;
227 clocks = <&k3_clks 154 0>;
233 reg = <0x00 0x02840000 0x00 0x100>;
236 clocks = <&k3_clks 155 0>;
242 reg = <0x00 0x02850000 0x00 0x100>;
245 clocks = <&k3_clks 156 0>;
251 reg = <0x00 0x02860000 0x00 0x100>;
254 clocks = <&k3_clks 158 0>;
260 reg = <0x00 0x20000000 0x00 0x100>;
263 #size-cells = <0>;
271 reg = <0x00 0x20010000 0x00 0x100>;
274 #size-cells = <0>;
282 reg = <0x00 0x20020000 0x00 0x100>;
285 #size-cells = <0>;
293 reg = <0x00 0x20030000 0x00 0x100>;
296 #size-cells = <0>;
304 reg = <0x00 0x20100000 0x00 0x400>;
307 #size-cells = <0>;
309 clocks = <&k3_clks 172 0>;
314 reg = <0x00 0x20110000 0x00 0x400>;
317 #size-cells = <0>;
319 clocks = <&k3_clks 173 0>;
324 reg = <0x00 0x20120000 0x00 0x400>;
327 #size-cells = <0>;
329 clocks = <&k3_clks 174 0>;
334 reg = <0x00 0x00a00000 0x00 0x800>;
341 ti,interrupt-ranges = <0 32 16>;
346 reg = <0x0 0x00600000 0x0 0x100>;
355 ti,davinci-gpio-unbanked = <0>;
357 clocks = <&k3_clks 77 0>;
363 reg = <0x0 0x00601000 0x0 0x100>;
372 ti,davinci-gpio-unbanked = <0>;
374 clocks = <&k3_clks 78 0>;
380 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
389 ti,trm-icp = <0x2>;
391 ti,clkbuf-sel = <0x7>;
392 ti,otap-del-sel-legacy = <0x0>;
393 ti,otap-del-sel-mmc-hs = <0x0>;
394 ti,otap-del-sel-ddr52 = <0x9>;
395 ti,otap-del-sel-hs200 = <0x6>;
400 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
405 ti,trm-icp = <0x2>;
406 ti,otap-del-sel-legacy = <0x0>;
407 ti,otap-del-sel-sd-hs = <0x0>;
408 ti,otap-del-sel-sdr12 = <0xf>;
409 ti,otap-del-sel-sdr25 = <0xf>;
410 ti,otap-del-sel-sdr50 = <0xc>;
411 ti,otap-del-sel-sdr104 = <0x6>;
412 ti,otap-del-sel-ddr50 = <0x9>;
413 ti,itap-del-sel-legacy = <0x0>;
414 ti,itap-del-sel-sd-hs = <0x0>;
415 ti,itap-del-sel-sdr12 = <0x0>;
416 ti,itap-del-sel-sdr25 = <0x0>;
417 ti,clkbuf-sel = <0x7>;
423 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
428 ti,trm-icp = <0x2>;
429 ti,otap-del-sel-legacy = <0x0>;
430 ti,otap-del-sel-sd-hs = <0x0>;
431 ti,otap-del-sel-sdr12 = <0xf>;
432 ti,otap-del-sel-sdr25 = <0xf>;
433 ti,otap-del-sel-sdr50 = <0xc>;
434 ti,otap-del-sel-sdr104 = <0x6>;
435 ti,otap-del-sel-ddr50 = <0x9>;
436 ti,itap-del-sel-legacy = <0x0>;
437 ti,itap-del-sel-sd-hs = <0x0>;
438 ti,itap-del-sel-sdr12 = <0x0>;
439 ti,itap-del-sel-sdr25 = <0x0>;
440 ti,clkbuf-sel = <0x7>;
445 reg = <0x00 0x0fc00000 0x00 0x70000>;
452 reg = <0x00 0x0fc40000 0x00 0x100>,
453 <0x05 0x00000000 0x01 0x00000000>;
457 cdns,trigger-address = <0x0>;
464 #size-cells = <0>;
472 reg = <0x00 0x08000000 0x00 0x200000>;
474 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
475 clocks = <&k3_clks 13 0>;
481 dmas = <&main_pktdma 0xc600 15>,
482 <&main_pktdma 0xc601 15>,
483 <&main_pktdma 0xc602 15>,
484 <&main_pktdma 0xc603 15>,
485 <&main_pktdma 0xc604 15>,
486 <&main_pktdma 0xc605 15>,
487 <&main_pktdma 0xc606 15>,
488 <&main_pktdma 0xc607 15>,
489 <&main_pktdma 0x4600 15>;
495 #size-cells = <0>;
503 ti,syscon-efuse = <&wkup_conf 0x200>;
517 reg = <0x00 0xf00 0x00 0x100>;
519 #size-cells = <0>;
520 clocks = <&k3_clks 13 0>;
527 reg = <0x00 0x3d000 0x00 0x400>;
539 reg = <0x00 0x2a000000 0x00 0x1000>;
545 reg = <0x00 0x29000000 0x00 0x200>;
556 reg = <0x00 0x23100000 0x00 0x100>;
558 clocks = <&k3_clks 51 0>;
565 reg = <0x00 0x23110000 0x00 0x100>;
567 clocks = <&k3_clks 52 0>;
574 reg = <0x00 0x23120000 0x00 0x100>;
576 clocks = <&k3_clks 53 0>;
582 reg = <0x00 0x20701000 0x00 0x200>,
583 <0x00 0x20708000 0x00 0x8000>;
591 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
597 reg = <0x00 0x23000000 0x00 0x100>;
599 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
606 reg = <0x00 0x23010000 0x00 0x100>;
608 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
615 reg = <0x00 0x23020000 0x00 0x100>;
617 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;