Lines Matching +full:tmod +full:- +full:calibration
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
42 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 next-level-cache = <&l2>;
47 operating-points-v2 = <&cluster0_opp>;
48 #cooling-cells = <2>;
53 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 next-level-cache = <&l2>;
58 operating-points-v2 = <&cluster0_opp>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
69 operating-points-v2 = <&cluster0_opp>;
70 #cooling-cells = <2>;
75 compatible = "arm,cortex-a53";
78 enable-method = "psci";
79 next-level-cache = <&l2>;
80 operating-points-v2 = <&cluster0_opp>;
81 #cooling-cells = <2>;
84 l2: l2-cache {
89 cluster0_opp: opp-table {
90 compatible = "operating-points-v2";
91 opp-shared;
93 opp-250000000 {
94 opp-hz = /bits/ 64 <250000000>;
95 clock-latency-ns = <300>;
97 opp-325000000 {
98 opp-hz = /bits/ 64 <325000000>;
99 clock-latency-ns = <300>;
101 opp-500000000 {
102 opp-hz = /bits/ 64 <500000000>;
103 clock-latency-ns = <300>;
105 opp-650000000 {
106 opp-hz = /bits/ 64 <650000000>;
107 clock-latency-ns = <300>;
109 opp-666667000 {
110 opp-hz = /bits/ 64 <666667000>;
111 clock-latency-ns = <300>;
113 opp-866667000 {
114 opp-hz = /bits/ 64 <866667000>;
115 clock-latency-ns = <300>;
117 opp-1000000000 {
118 opp-hz = /bits/ 64 <1000000000>;
119 clock-latency-ns = <300>;
121 opp-1300000000 {
122 opp-hz = /bits/ 64 <1300000000>;
123 clock-latency-ns = <300>;
128 compatible = "arm,psci-1.0";
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <25000000>;
140 emmc_pwrseq: emmc-pwrseq {
141 compatible = "mmc-pwrseq-emmc";
142 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
146 compatible = "arm,armv8-timer";
153 thermal-zones {
154 cpu-thermal {
155 polling-delay-passive = <250>; /* 250ms */
156 polling-delay = <1000>; /* 1000ms */
157 thermal-sensors = <&pvtctl>;
160 cpu_crit: cpu-crit {
165 cpu_alert: cpu-alert {
172 cooling-maps {
175 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
184 reserved-memory {
185 #address-cells = <2>;
186 #size-cells = <2>;
189 secure-memory@81000000 {
191 no-map;
196 compatible = "simple-bus";
197 #address-cells = <1>;
198 #size-cells = <1>;
202 compatible = "socionext,uniphier-scssi";
205 #address-cells = <1>;
206 #size-cells = <0>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_spi0>;
215 compatible = "socionext,uniphier-scssi";
218 #address-cells = <1>;
219 #size-cells = <0>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_spi1>;
228 compatible = "socionext,uniphier-uart";
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart0>;
239 compatible = "socionext,uniphier-uart";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart1>;
250 compatible = "socionext,uniphier-uart";
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
261 compatible = "socionext,uniphier-uart";
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart3>;
272 compatible = "socionext,uniphier-gpio";
274 interrupt-parent = <&aidet>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 gpio-ranges = <&pinctrl 0 0 0>,
282 gpio-ranges-group-names = "gpio_range0",
286 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
291 compatible = "socionext,uniphier-fi2c";
294 #address-cells = <1>;
295 #size-cells = <0>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c0>;
301 clock-frequency = <100000>;
305 compatible = "socionext,uniphier-fi2c";
308 #address-cells = <1>;
309 #size-cells = <0>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_i2c1>;
315 clock-frequency = <100000>;
319 compatible = "socionext,uniphier-fi2c";
322 #address-cells = <1>;
323 #size-cells = <0>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_i2c2>;
329 clock-frequency = <100000>;
333 compatible = "socionext,uniphier-fi2c";
336 #address-cells = <1>;
337 #size-cells = <0>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_i2c3>;
343 clock-frequency = <100000>;
346 /* chip-internal connection for HDMI */
348 compatible = "socionext,uniphier-fi2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
355 clock-frequency = <400000>;
358 system_bus: system-bus@58c00000 {
359 compatible = "socionext,uniphier-system-bus";
362 #address-cells = <2>;
363 #size-cells = <1>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_system_bus>;
369 compatible = "socionext,uniphier-smpctrl";
374 compatible = "socionext,uniphier-pxs3-sdctrl",
375 "simple-mfd", "syscon";
379 compatible = "socionext,uniphier-pxs3-sd-clock";
380 #clock-cells = <1>;
384 compatible = "socionext,uniphier-pxs3-sd-reset";
385 #reset-cells = <1>;
390 compatible = "socionext,uniphier-pxs3-perictrl",
391 "simple-mfd", "syscon";
395 compatible = "socionext,uniphier-pxs3-peri-clock";
396 #clock-cells = <1>;
400 compatible = "socionext,uniphier-pxs3-peri-reset";
401 #reset-cells = <1>;
406 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_emmc>;
413 bus-width = <8>;
414 mmc-ddr-1_8v;
415 mmc-hs200-1_8v;
416 mmc-pwrseq = <&emmc_pwrseq>;
417 cdns,phy-input-delay-legacy = <9>;
418 cdns,phy-input-delay-mmc-highspeed = <2>;
419 cdns,phy-input-delay-mmc-ddr = <3>;
420 cdns,phy-dll-delay-sdclk = <21>;
421 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
425 compatible = "socionext,uniphier-sd-v3.1.1";
429 pinctrl-names = "default", "uhs";
430 pinctrl-0 = <&pinctrl_sd>;
431 pinctrl-1 = <&pinctrl_sd_uhs>;
433 reset-names = "host";
435 bus-width = <4>;
436 cap-sd-highspeed;
437 sd-uhs-sdr12;
438 sd-uhs-sdr25;
439 sd-uhs-sdr50;
442 soc_glue: soc-glue@5f800000 {
443 compatible = "socionext,uniphier-pxs3-soc-glue",
444 "simple-mfd", "syscon";
448 compatible = "socionext,uniphier-pxs3-pinctrl";
452 soc-glue@5f900000 {
453 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
454 "simple-mfd";
455 #address-cells = <1>;
456 #size-cells = <1>;
460 compatible = "socionext,uniphier-efuse";
465 compatible = "socionext,uniphier-efuse";
467 #address-cells = <1>;
468 #size-cells = <1>;
514 xdmac: dma-controller@5fc10000 {
515 compatible = "socionext,uniphier-xdmac";
518 dma-channels = <16>;
519 #dma-cells = <2>;
522 aidet: interrupt-controller@5fc20000 {
523 compatible = "socionext,uniphier-pxs3-aidet";
525 interrupt-controller;
526 #interrupt-cells = <2>;
529 gic: interrupt-controller@5fe00000 {
530 compatible = "arm,gic-v3";
533 interrupt-controller;
534 #interrupt-cells = <3>;
539 compatible = "socionext,uniphier-pxs3-sysctrl",
540 "simple-mfd", "syscon";
544 compatible = "socionext,uniphier-pxs3-clock";
545 #clock-cells = <1>;
549 compatible = "socionext,uniphier-pxs3-reset";
550 #reset-cells = <1>;
554 compatible = "socionext,uniphier-wdt";
557 pvtctl: thermal-sensor {
558 compatible = "socionext,uniphier-pxs3-thermal";
560 #thermal-sensor-cells = <0>;
561 socionext,tmod-calibration = <0x0f22 0x68ee>;
566 compatible = "socionext,uniphier-pxs3-ave4";
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_ether_rgmii>;
572 clock-names = "ether";
574 reset-names = "ether";
576 phy-mode = "rgmii-id";
577 local-mac-address = [00 00 00 00 00 00];
578 socionext,syscon-phy-mode = <&soc_glue 0>;
581 #address-cells = <1>;
582 #size-cells = <0>;
587 compatible = "socionext,uniphier-pxs3-ave4";
591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_ether1_rgmii>;
593 clock-names = "ether";
595 reset-names = "ether";
597 phy-mode = "rgmii-id";
598 local-mac-address = [00 00 00 00 00 00];
599 socionext,syscon-phy-mode = <&soc_glue 1>;
602 #address-cells = <1>;
603 #size-cells = <0>;
608 compatible = "socionext,uniphier-pxs3-ahci",
609 "generic-ahci";
615 ports-implemented = <1>;
619 sata-controller@65700000 {
620 compatible = "socionext,uniphier-pxs3-ahci-glue",
621 "simple-mfd";
622 #address-cells = <1>;
623 #size-cells = <1>;
626 ahci0_rst: reset-controller@0 {
627 compatible = "socionext,uniphier-pxs3-ahci-reset";
629 clock-names = "link";
631 reset-names = "link";
633 #reset-cells = <1>;
636 ahci0_phy: sata-phy@10 {
637 compatible = "socionext,uniphier-pxs3-ahci-phy";
639 clock-names = "link", "phy";
641 reset-names = "link", "phy";
643 #phy-cells = <0>;
648 compatible = "socionext,uniphier-pxs3-ahci",
649 "generic-ahci";
655 ports-implemented = <1>;
659 sata-controller@65900000 {
660 compatible = "socionext,uniphier-pxs3-ahci-glue",
661 "simple-mfd";
662 #address-cells = <1>;
663 #size-cells = <1>;
666 ahci1_rst: reset-controller@0 {
667 compatible = "socionext,uniphier-pxs3-ahci-reset";
669 clock-names = "link";
671 reset-names = "link";
673 #reset-cells = <1>;
676 ahci1_phy: sata-phy@10 {
677 compatible = "socionext,uniphier-pxs3-ahci-phy";
679 clock-names = "link", "phy";
681 reset-names = "link", "phy";
683 #phy-cells = <0>;
688 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
691 interrupt-names = "dwc_usb3";
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
695 clock-names = "ref", "bus_early", "suspend";
703 usb-controller@65b00000 {
704 compatible = "socionext,uniphier-pxs3-dwc3-glue",
705 "simple-mfd";
706 #address-cells = <1>;
707 #size-cells = <1>;
711 compatible = "socionext,uniphier-pxs3-usb3-reset";
713 #reset-cells = <1>;
714 clock-names = "link";
716 reset-names = "link";
721 compatible = "socionext,uniphier-pxs3-usb3-regulator";
723 clock-names = "link";
725 reset-names = "link";
730 compatible = "socionext,uniphier-pxs3-usb3-regulator";
732 clock-names = "link";
734 reset-names = "link";
738 usb0_hsphy0: hs-phy@200 {
739 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
741 #phy-cells = <0>;
742 clock-names = "link", "phy";
744 reset-names = "link", "phy";
746 vbus-supply = <&usb0_vbus0>;
747 nvmem-cell-names = "rterm", "sel_t", "hs_i";
748 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
752 usb0_hsphy1: hs-phy@210 {
753 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
755 #phy-cells = <0>;
756 clock-names = "link", "phy";
758 reset-names = "link", "phy";
760 vbus-supply = <&usb0_vbus1>;
761 nvmem-cell-names = "rterm", "sel_t", "hs_i";
762 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
766 usb0_ssphy0: ss-phy@300 {
767 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
769 #phy-cells = <0>;
770 clock-names = "link", "phy";
772 reset-names = "link", "phy";
774 vbus-supply = <&usb0_vbus0>;
777 usb0_ssphy1: ss-phy@310 {
778 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
780 #phy-cells = <0>;
781 clock-names = "link", "phy";
783 reset-names = "link", "phy";
785 vbus-supply = <&usb0_vbus1>;
790 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
793 interrupt-names = "dwc_usb3";
795 pinctrl-names = "default";
796 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
797 clock-names = "ref", "bus_early", "suspend";
805 usb-controller@65d00000 {
806 compatible = "socionext,uniphier-pxs3-dwc3-glue",
807 "simple-mfd";
808 #address-cells = <1>;
809 #size-cells = <1>;
813 compatible = "socionext,uniphier-pxs3-usb3-reset";
815 #reset-cells = <1>;
816 clock-names = "link";
818 reset-names = "link";
823 compatible = "socionext,uniphier-pxs3-usb3-regulator";
825 clock-names = "link";
827 reset-names = "link";
832 compatible = "socionext,uniphier-pxs3-usb3-regulator";
834 clock-names = "link";
836 reset-names = "link";
840 usb1_hsphy0: hs-phy@200 {
841 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
843 #phy-cells = <0>;
844 clock-names = "link", "phy", "phy-ext";
847 reset-names = "link", "phy";
849 vbus-supply = <&usb1_vbus0>;
850 nvmem-cell-names = "rterm", "sel_t", "hs_i";
851 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
855 usb1_hsphy1: hs-phy@210 {
856 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
858 #phy-cells = <0>;
859 clock-names = "link", "phy", "phy-ext";
862 reset-names = "link", "phy";
864 vbus-supply = <&usb1_vbus1>;
865 nvmem-cell-names = "rterm", "sel_t", "hs_i";
866 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
870 usb1_ssphy0: ss-phy@300 {
871 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
873 #phy-cells = <0>;
874 clock-names = "link", "phy", "phy-ext";
877 reset-names = "link", "phy";
879 vbus-supply = <&usb1_vbus0>;
884 compatible = "socionext,uniphier-pcie";
886 reg-names = "dbi", "link", "config";
889 #address-cells = <3>;
890 #size-cells = <2>;
893 num-lanes = <1>;
894 num-viewport = <1>;
895 bus-range = <0x0 0xff>;
900 /* non-prefetchable memory */
902 #interrupt-cells = <1>;
903 interrupt-names = "dma", "msi";
906 interrupt-map-mask = <0 0 0 7>;
907 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
911 phy-names = "pcie-phy";
914 pcie_intc: legacy-interrupt-controller {
915 interrupt-controller;
916 #interrupt-cells = <1>;
917 interrupt-parent = <&gic>;
923 compatible = "socionext,uniphier-pxs3-pcie-phy";
925 #phy-cells = <0>;
926 clock-names = "link";
928 reset-names = "link";
933 nand: nand-controller@68000000 {
934 compatible = "socionext,uniphier-denali-nand-v5b";
936 reg-names = "nand_data", "denali_reg";
938 #address-cells = <1>;
939 #size-cells = <0>;
941 pinctrl-names = "default";
942 pinctrl-0 = <&pinctrl_nand>;
943 clock-names = "nand", "nand_x", "ecc";
945 reset-names = "nand", "reg";
951 #include "uniphier-pinctrl.dtsi"