Lines Matching +full:0 +full:x5a000000
21 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0 0x000>;
57 reg = <0 0x001>;
68 reg = <0 0x100>;
79 reg = <0 0x101>;
96 cluster0_opp: opp-table-0 {
180 #clock-cells = <0>;
235 reg = <0x0 0x81000000 0x0 0x01000000>;
240 soc@0 {
244 ranges = <0 0 0 0xffffffff>;
249 reg = <0x54006000 0x100>;
251 #size-cells = <0>;
254 pinctrl-0 = <&pinctrl_spi0>;
262 reg = <0x54006100 0x100>;
264 #size-cells = <0>;
267 pinctrl-0 = <&pinctrl_spi1>;
275 reg = <0x54006200 0x100>;
277 #size-cells = <0>;
280 pinctrl-0 = <&pinctrl_spi2>;
288 reg = <0x54006300 0x100>;
290 #size-cells = <0>;
293 pinctrl-0 = <&pinctrl_spi3>;
301 reg = <0x54006800 0x40>;
304 pinctrl-0 = <&pinctrl_uart0>;
305 clocks = <&peri_clk 0>;
306 resets = <&peri_rst 0>;
312 reg = <0x54006900 0x40>;
315 pinctrl-0 = <&pinctrl_uart1>;
323 reg = <0x54006a00 0x40>;
326 pinctrl-0 = <&pinctrl_uart2>;
334 reg = <0x54006b00 0x40>;
337 pinctrl-0 = <&pinctrl_uart3>;
344 reg = <0x55000000 0x200>;
350 gpio-ranges = <&pinctrl 0 0 0>,
351 <&pinctrl 96 0 0>,
352 <&pinctrl 160 0 0>;
357 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
363 reg = <0x56000000 0x80000>;
366 pinctrl-0 = <&pinctrl_aout1>,
375 i2s_port0: port@0 {
427 reg = <0x57900000 0x1000>;
431 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
434 port@0 {
450 reg = <0x57920000 0x1000>;
461 reg = <0x58780000 0x80>;
463 #size-cells = <0>;
466 pinctrl-0 = <&pinctrl_i2c0>;
475 reg = <0x58781000 0x80>;
477 #size-cells = <0>;
480 pinctrl-0 = <&pinctrl_i2c1>;
488 reg = <0x58782000 0x80>;
490 #size-cells = <0>;
500 reg = <0x58783000 0x80>;
502 #size-cells = <0>;
505 pinctrl-0 = <&pinctrl_i2c3>;
514 reg = <0x58784000 0x80>;
516 #size-cells = <0>;
519 pinctrl-0 = <&pinctrl_i2c4>;
527 reg = <0x58785000 0x80>;
529 #size-cells = <0>;
539 reg = <0x58c00000 0x400>;
543 pinctrl-0 = <&pinctrl_system_bus>;
548 reg = <0x59801000 0x400>;
554 reg = <0x59810000 0x400>;
570 reg = <0x59820000 0x200>;
585 reg = <0x5a000000 0x400>;
588 pinctrl-0 = <&pinctrl_emmc>;
605 reg = <0x5a400000 0x800>;
608 pinctrl-0 = <&pinctrl_sd>;
609 clocks = <&sd_clk 0>;
611 resets = <&sd_rst 0>;
619 reg = <0x5f800000 0x2000>;
631 ranges = <0 0x5f900000 0x2000>;
635 reg = <0x100 0x28>;
640 reg = <0x200 0x68>;
646 reg = <0x54 1>;
650 reg = <0x55 1>;
654 reg = <0x58 1>;
658 reg = <0x59 1>;
661 usb_sel_t0: trim@54,0 {
662 reg = <0x54 1>;
663 bits = <0 4>;
665 usb_sel_t1: trim@55,0 {
666 reg = <0x55 1>;
667 bits = <0 4>;
669 usb_sel_t2: trim@58,0 {
670 reg = <0x58 1>;
671 bits = <0 4>;
673 usb_sel_t3: trim@59,0 {
674 reg = <0x59 1>;
675 bits = <0 4>;
677 usb_hs_i0: trim@56,0 {
678 reg = <0x56 1>;
679 bits = <0 4>;
681 usb_hs_i2: trim@5a,0 {
682 reg = <0x5a 1>;
683 bits = <0 4>;
690 reg = <0x5fc10000 0x5300>;
698 reg = <0x5fc20000 0x200>;
705 reg = <0x5fe00000 0x10000>, /* GICD */
706 <0x5fe80000 0x80000>; /* GICR */
715 reg = <0x61840000 0x10000>;
734 #thermal-sensor-cells = <0>;
735 socionext,tmod-calibration = <0x0f22 0x68ee>;
742 reg = <0x65000000 0x8500>;
745 pinctrl-0 = <&pinctrl_ether_rgmii>;
752 socionext,syscon-phy-mode = <&soc_glue 0>;
756 #size-cells = <0>;
763 reg = <0x65a00000 0xcd00>;
767 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
783 ranges = <0 0x65b00000 0x400>;
785 usb_rst: reset@0 {
787 reg = <0x0 0x4>;
797 reg = <0x100 0x10>;
806 reg = <0x110 0x10>;
815 reg = <0x120 0x10>;
824 reg = <0x130 0x10>;
833 reg = <0x200 0x10>;
834 #phy-cells = <0>;
847 reg = <0x210 0x10>;
848 #phy-cells = <0>;
861 reg = <0x220 0x10>;
862 #phy-cells = <0>;
875 reg = <0x230 0x10>;
876 #phy-cells = <0>;
889 reg = <0x300 0x10>;
890 #phy-cells = <0>;
900 reg = <0x310 0x10>;
901 #phy-cells = <0>;
914 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
915 <0x2fff0000 0x10000>;
922 bus-range = <0x0 0xff>;
926 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
928 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
933 interrupt-map-mask = <0 0 0 7>;
934 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
935 <0 0 0 2 &pcie_intc 1>, /* INTB */
936 <0 0 0 3 &pcie_intc 2>, /* INTC */
937 <0 0 0 4 &pcie_intc 3>; /* INTD */
951 reg = <0x66038000 0x4000>;
952 #phy-cells = <0>;
964 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
966 #size-cells = <0>;
969 pinctrl-0 = <&pinctrl_nand>;