Lines Matching +full:phy +full:- +full:grf
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
64 compatible = "arm,cortex-a55";
66 #cooling-cells = <2>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
73 compatible = "arm,cortex-a55";
75 #cooling-cells = <2>;
76 enable-method = "psci";
77 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a55";
84 #cooling-cells = <2>;
85 enable-method = "psci";
86 operating-points-v2 = <&cpu0_opp_table>;
90 cpu0_opp_table: opp-table-0 {
91 compatible = "operating-points-v2";
92 opp-shared;
94 opp-408000000 {
95 opp-hz = /bits/ 64 <408000000>;
96 opp-microvolt = <900000 900000 1150000>;
97 clock-latency-ns = <40000>;
100 opp-600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <900000 900000 1150000>;
105 opp-816000000 {
106 opp-hz = /bits/ 64 <816000000>;
107 opp-microvolt = <900000 900000 1150000>;
108 opp-suspend;
111 opp-1104000000 {
112 opp-hz = /bits/ 64 <1104000000>;
113 opp-microvolt = <900000 900000 1150000>;
116 opp-1416000000 {
117 opp-hz = /bits/ 64 <1416000000>;
118 opp-microvolt = <900000 900000 1150000>;
121 opp-1608000000 {
122 opp-hz = /bits/ 64 <1608000000>;
123 opp-microvolt = <975000 975000 1150000>;
126 opp-1800000000 {
127 opp-hz = /bits/ 64 <1800000000>;
128 opp-microvolt = <1050000 1050000 1150000>;
132 display_subsystem: display-subsystem {
133 compatible = "rockchip,display-subsystem";
139 compatible = "arm,scmi-smc";
140 arm,smc-id = <0x82000010>;
142 #address-cells = <1>;
143 #size-cells = <0>;
147 #clock-cells = <1>;
152 gpu_opp_table: opp-table-1 {
153 compatible = "operating-points-v2";
155 opp-200000000 {
156 opp-hz = /bits/ 64 <200000000>;
157 opp-microvolt = <825000>;
160 opp-300000000 {
161 opp-hz = /bits/ 64 <300000000>;
162 opp-microvolt = <825000>;
165 opp-400000000 {
166 opp-hz = /bits/ 64 <400000000>;
167 opp-microvolt = <825000>;
170 opp-600000000 {
171 opp-hz = /bits/ 64 <600000000>;
172 opp-microvolt = <825000>;
175 opp-700000000 {
176 opp-hz = /bits/ 64 <700000000>;
177 opp-microvolt = <900000>;
180 opp-800000000 {
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <1000000>;
186 hdmi_sound: hdmi-sound {
187 compatible = "simple-audio-card";
188 simple-audio-card,name = "HDMI";
189 simple-audio-card,format = "i2s";
190 simple-audio-card,mclk-fs = <256>;
193 simple-audio-card,codec {
194 sound-dai = <&hdmi>;
197 simple-audio-card,cpu {
198 sound-dai = <&i2s0_8ch>;
203 compatible = "arm,cortex-a55-pmu";
208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
212 compatible = "arm,psci-1.0";
217 compatible = "arm,armv8-timer";
222 arm,no-tick-in-suspend;
226 compatible = "fixed-clock";
227 clock-frequency = <24000000>;
228 clock-output-names = "xin24m";
229 #clock-cells = <0>;
233 compatible = "fixed-clock";
234 clock-frequency = <32768>;
235 clock-output-names = "xin32k";
236 pinctrl-0 = <&clk32k_out0>;
237 pinctrl-names = "default";
238 #clock-cells = <0>;
242 compatible = "mmio-sram";
244 #address-cells = <1>;
245 #size-cells = <1>;
249 compatible = "arm,scmi-shmem";
255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
259 clock-names = "sata", "pmalive", "rxoob";
262 phy-names = "sata-phy";
263 ports-implemented = <0x1>;
264 power-domains = <&power RK3568_PD_PIPE>;
269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
273 clock-names = "sata", "pmalive", "rxoob";
276 phy-names = "sata-phy";
277 ports-implemented = <0x1>;
278 power-domains = <&power RK3568_PD_PIPE>;
283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
288 clock-names = "ref_clk", "suspend_clk",
292 power-domains = <&power RK3568_PD_PIPE>;
299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
304 clock-names = "ref_clk", "suspend_clk",
308 phy-names = "usb2-phy", "usb3-phy";
310 power-domains = <&power RK3568_PD_PIPE>;
316 gic: interrupt-controller@fd400000 {
317 compatible = "arm,gic-v3";
321 interrupt-controller;
322 #interrupt-cells = <3>;
323 mbi-alias = <0x0 0xfd410000>;
324 mbi-ranges = <296 24>;
325 msi-controller;
329 compatible = "generic-ehci";
335 phy-names = "usb";
340 compatible = "generic-ohci";
346 phy-names = "usb";
351 compatible = "generic-ehci";
357 phy-names = "usb";
362 compatible = "generic-ohci";
368 phy-names = "usb";
373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
376 pmu_io_domains: io-domains {
377 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
386 grf: syscon@fdc60000 { label
387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
411 pmucru: clock-controller@fdd00000 {
412 compatible = "rockchip,rk3568-pmucru";
414 #clock-cells = <1>;
415 #reset-cells = <1>;
418 cru: clock-controller@fdd20000 {
419 compatible = "rockchip,rk3568-cru";
422 clock-names = "xin24m";
423 #clock-cells = <1>;
424 #reset-cells = <1>;
425 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
426 assigned-clock-rates = <1200000000>, <200000000>;
427 rockchip,grf = <&grf>;
431 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
435 clock-names = "i2c", "pclk";
436 pinctrl-0 = <&i2c0_xfer>;
437 pinctrl-names = "default";
438 #address-cells = <1>;
439 #size-cells = <0>;
444 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
448 clock-names = "baudclk", "apb_pclk";
450 pinctrl-0 = <&uart0_xfer>;
451 pinctrl-names = "default";
452 reg-io-width = <4>;
453 reg-shift = <2>;
458 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
461 clock-names = "pwm", "pclk";
462 pinctrl-0 = <&pwm0m0_pins>;
463 pinctrl-names = "default";
464 #pwm-cells = <3>;
469 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
472 clock-names = "pwm", "pclk";
473 pinctrl-0 = <&pwm1m0_pins>;
474 pinctrl-names = "default";
475 #pwm-cells = <3>;
480 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
483 clock-names = "pwm", "pclk";
484 pinctrl-0 = <&pwm2m0_pins>;
485 pinctrl-names = "default";
486 #pwm-cells = <3>;
491 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
494 clock-names = "pwm", "pclk";
495 pinctrl-0 = <&pwm3_pins>;
496 pinctrl-names = "default";
497 #pwm-cells = <3>;
501 pmu: power-management@fdd90000 {
502 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
505 power: power-controller {
506 compatible = "rockchip,rk3568-power-controller";
507 #power-domain-cells = <1>;
508 #address-cells = <1>;
509 #size-cells = <0>;
512 power-domain@RK3568_PD_GPU {
517 #power-domain-cells = <0>;
521 power-domain@RK3568_PD_VI {
528 #power-domain-cells = <0>;
531 power-domain@RK3568_PD_VO {
539 #power-domain-cells = <0>;
542 power-domain@RK3568_PD_RGA {
552 #power-domain-cells = <0>;
555 power-domain@RK3568_PD_VPU {
559 #power-domain-cells = <0>;
562 power-domain@RK3568_PD_RKVDEC {
566 #power-domain-cells = <0>;
569 power-domain@RK3568_PD_RKVENC {
575 #power-domain-cells = <0>;
581 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
586 interrupt-names = "job", "mmu", "gpu";
588 clock-names = "gpu", "bus";
589 #cooling-cells = <2>;
590 operating-points-v2 = <&gpu_opp_table>;
591 power-domains = <&power RK3568_PD_GPU>;
595 vpu: video-codec@fdea0400 {
596 compatible = "rockchip,rk3568-vpu";
600 clock-names = "aclk", "hclk";
602 power-domains = <&power RK3568_PD_VPU>;
606 compatible = "rockchip,rk3568-iommu";
609 clock-names = "aclk", "iface";
611 power-domains = <&power RK3568_PD_VPU>;
612 #iommu-cells = <0>;
615 vepu: video-codec@fdee0000 {
616 compatible = "rockchip,rk3568-vepu";
620 clock-names = "aclk", "hclk";
622 power-domains = <&power RK3568_PD_RGA>;
626 compatible = "rockchip,rk3568-iommu";
630 clock-names = "aclk", "iface";
631 power-domains = <&power RK3568_PD_RGA>;
632 #iommu-cells = <0>;
636 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
641 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
642 fifo-depth = <0x100>;
643 max-frequency = <150000000>;
645 reset-names = "reset";
650 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
654 interrupt-names = "macirq", "eth_wake_irq";
659 clock-names = "stmmaceth", "mac_clk_rx",
664 reset-names = "stmmaceth";
665 rockchip,grf = <&grf>;
666 snps,axi-config = <&gmac1_stmmac_axi_setup>;
667 snps,mixed-burst;
668 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
669 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
674 compatible = "snps,dwmac-mdio";
675 #address-cells = <0x1>;
676 #size-cells = <0x0>;
679 gmac1_stmmac_axi_setup: stmmac-axi-config {
685 gmac1_mtl_rx_setup: rx-queues-config {
686 snps,rx-queues-to-use = <1>;
690 gmac1_mtl_tx_setup: tx-queues-config {
691 snps,tx-queues-to-use = <1>;
698 reg-names = "vop", "gamma-lut";
702 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
704 power-domains = <&power RK3568_PD_VO>;
705 rockchip,grf = <&grf>;
709 #address-cells = <1>;
710 #size-cells = <0>;
714 #address-cells = <1>;
715 #size-cells = <0>;
720 #address-cells = <1>;
721 #size-cells = <0>;
726 #address-cells = <1>;
727 #size-cells = <0>;
733 compatible = "rockchip,rk3568-iommu";
737 clock-names = "aclk", "iface";
738 #iommu-cells = <0>;
743 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
746 clock-names = "pclk", "hclk";
748 phy-names = "dphy";
750 power-domains = <&power RK3568_PD_VO>;
751 reset-names = "apb";
753 rockchip,grf = <&grf>;
757 #address-cells = <1>;
758 #size-cells = <0>;
771 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
774 clock-names = "pclk", "hclk";
776 phy-names = "dphy";
778 power-domains = <&power RK3568_PD_VO>;
779 reset-names = "apb";
781 rockchip,grf = <&grf>;
785 #address-cells = <1>;
786 #size-cells = <0>;
799 compatible = "rockchip,rk3568-dw-hdmi";
807 clock-names = "iahb", "isfr", "cec", "ref";
808 pinctrl-names = "default";
809 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
810 power-domains = <&power RK3568_PD_VO>;
811 reg-io-width = <4>;
812 rockchip,grf = <&grf>;
813 #sound-dai-cells = <0>;
817 #address-cells = <1>;
818 #size-cells = <0>;
831 compatible = "rockchip,rk3568-qos", "syscon";
836 compatible = "rockchip,rk3568-qos", "syscon";
841 compatible = "rockchip,rk3568-qos", "syscon";
846 compatible = "rockchip,rk3568-qos", "syscon";
851 compatible = "rockchip,rk3568-qos", "syscon";
856 compatible = "rockchip,rk3568-qos", "syscon";
861 compatible = "rockchip,rk3568-qos", "syscon";
866 compatible = "rockchip,rk3568-qos", "syscon";
871 compatible = "rockchip,rk3568-qos", "syscon";
876 compatible = "rockchip,rk3568-qos", "syscon";
881 compatible = "rockchip,rk3568-qos", "syscon";
886 compatible = "rockchip,rk3568-qos", "syscon";
891 compatible = "rockchip,rk3568-qos", "syscon";
896 compatible = "rockchip,rk3568-qos", "syscon";
901 compatible = "rockchip,rk3568-qos", "syscon";
906 compatible = "rockchip,rk3568-qos", "syscon";
911 compatible = "rockchip,rk3568-qos", "syscon";
916 compatible = "rockchip,rk3568-qos", "syscon";
921 compatible = "rockchip,rk3568-qos", "syscon";
926 compatible = "rockchip,rk3568-qos", "syscon";
931 compatible = "rockchip,rk3568-qos", "syscon";
936 compatible = "rockchip,rk3568-qos", "syscon";
941 compatible = "rockchip,rk3568-qos", "syscon";
946 compatible = "rockchip,rk3568-qos", "syscon";
951 compatible = "rockchip,rk3568-pcie";
955 reg-names = "dbi", "apb", "config";
961 interrupt-names = "sys", "pmc", "msi", "legacy", "err";
962 bus-range = <0x0 0xf>;
966 clock-names = "aclk_mst", "aclk_slv",
969 interrupt-map-mask = <0 0 0 7>;
970 interrupt-map = <0 0 0 1 &pcie_intc 0>,
974 linux,pci-domain = <0>;
975 num-ib-windows = <6>;
976 num-ob-windows = <2>;
977 max-link-speed = <2>;
978 msi-map = <0x0 &gic 0x0 0x1000>;
979 num-lanes = <1>;
981 phy-names = "pcie-phy";
982 power-domains = <&power RK3568_PD_PIPE>;
986 reset-names = "pipe";
987 #address-cells = <3>;
988 #size-cells = <2>;
991 pcie_intc: legacy-interrupt-controller {
992 #address-cells = <0>;
993 #interrupt-cells = <1>;
994 interrupt-controller;
995 interrupt-parent = <&gic>;
1001 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1006 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1007 fifo-depth = <0x100>;
1008 max-frequency = <150000000>;
1010 reset-names = "reset";
1015 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1020 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1021 fifo-depth = <0x100>;
1022 max-frequency = <150000000>;
1024 reset-names = "reset";
1033 clock-names = "clk_sfc", "hclk_sfc";
1034 pinctrl-0 = <&fspi_pins>;
1035 pinctrl-names = "default";
1040 compatible = "rockchip,rk3568-dwcmshc";
1043 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1044 assigned-clock-rates = <200000000>, <24000000>;
1048 clock-names = "core", "bus", "axi", "block", "timer";
1053 compatible = "rockchip,rk3568-spdif";
1056 clock-names = "mclk", "hclk";
1059 dma-names = "tx";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&spdifm0_tx>;
1062 #sound-dai-cells = <0>;
1067 compatible = "rockchip,rk3568-i2s-tdm";
1070 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1071 assigned-clock-rates = <1188000000>, <1188000000>;
1073 clock-names = "mclk_tx", "mclk_rx", "hclk";
1075 dma-names = "tx";
1077 reset-names = "tx-m", "rx-m";
1078 rockchip,grf = <&grf>;
1079 #sound-dai-cells = <0>;
1084 compatible = "rockchip,rk3568-i2s-tdm";
1087 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1088 assigned-clock-rates = <1188000000>, <1188000000>;
1091 clock-names = "mclk_tx", "mclk_rx", "hclk";
1093 dma-names = "rx", "tx";
1095 reset-names = "tx-m", "rx-m";
1096 rockchip,grf = <&grf>;
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1104 #sound-dai-cells = <0>;
1109 compatible = "rockchip,rk3568-i2s-tdm";
1114 clock-names = "mclk_tx", "mclk_rx", "hclk";
1116 dma-names = "tx", "rx";
1118 reset-names = "tx-m", "rx-m";
1119 rockchip,grf = <&grf>;
1120 #sound-dai-cells = <0>;
1125 compatible = "rockchip,rk3568-pdm";
1129 clock-names = "pdm_clk", "pdm_hclk";
1131 dma-names = "rx";
1132 pinctrl-0 = <&pdmm0_clk
1138 pinctrl-names = "default";
1140 reset-names = "pdm-m";
1141 #sound-dai-cells = <0>;
1145 dmac0: dma-controller@fe530000 {
1150 arm,pl330-periph-burst;
1152 clock-names = "apb_pclk";
1153 #dma-cells = <1>;
1156 dmac1: dma-controller@fe550000 {
1161 arm,pl330-periph-burst;
1163 clock-names = "apb_pclk";
1164 #dma-cells = <1>;
1168 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1172 clock-names = "i2c", "pclk";
1173 pinctrl-0 = <&i2c1_xfer>;
1174 pinctrl-names = "default";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1185 clock-names = "i2c", "pclk";
1186 pinctrl-0 = <&i2c2m0_xfer>;
1187 pinctrl-names = "default";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1194 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1198 clock-names = "i2c", "pclk";
1199 pinctrl-0 = <&i2c3m0_xfer>;
1200 pinctrl-names = "default";
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1207 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1211 clock-names = "i2c", "pclk";
1212 pinctrl-0 = <&i2c4m0_xfer>;
1213 pinctrl-names = "default";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1220 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1224 clock-names = "i2c", "pclk";
1225 pinctrl-0 = <&i2c5m0_xfer>;
1226 pinctrl-names = "default";
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1233 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1237 clock-names = "tclk", "pclk";
1241 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1245 clock-names = "spiclk", "apb_pclk";
1247 dma-names = "tx", "rx";
1248 pinctrl-names = "default";
1249 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1256 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1260 clock-names = "spiclk", "apb_pclk";
1262 dma-names = "tx", "rx";
1263 pinctrl-names = "default";
1264 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1271 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1275 clock-names = "spiclk", "apb_pclk";
1277 dma-names = "tx", "rx";
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1290 clock-names = "spiclk", "apb_pclk";
1292 dma-names = "tx", "rx";
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1295 #address-cells = <1>;
1296 #size-cells = <0>;
1301 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1305 clock-names = "baudclk", "apb_pclk";
1307 pinctrl-0 = <&uart1m0_xfer>;
1308 pinctrl-names = "default";
1309 reg-io-width = <4>;
1310 reg-shift = <2>;
1315 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1319 clock-names = "baudclk", "apb_pclk";
1321 pinctrl-0 = <&uart2m0_xfer>;
1322 pinctrl-names = "default";
1323 reg-io-width = <4>;
1324 reg-shift = <2>;
1329 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1333 clock-names = "baudclk", "apb_pclk";
1335 pinctrl-0 = <&uart3m0_xfer>;
1336 pinctrl-names = "default";
1337 reg-io-width = <4>;
1338 reg-shift = <2>;
1343 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1347 clock-names = "baudclk", "apb_pclk";
1349 pinctrl-0 = <&uart4m0_xfer>;
1350 pinctrl-names = "default";
1351 reg-io-width = <4>;
1352 reg-shift = <2>;
1357 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1361 clock-names = "baudclk", "apb_pclk";
1363 pinctrl-0 = <&uart5m0_xfer>;
1364 pinctrl-names = "default";
1365 reg-io-width = <4>;
1366 reg-shift = <2>;
1371 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1375 clock-names = "baudclk", "apb_pclk";
1377 pinctrl-0 = <&uart6m0_xfer>;
1378 pinctrl-names = "default";
1379 reg-io-width = <4>;
1380 reg-shift = <2>;
1385 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1389 clock-names = "baudclk", "apb_pclk";
1391 pinctrl-0 = <&uart7m0_xfer>;
1392 pinctrl-names = "default";
1393 reg-io-width = <4>;
1394 reg-shift = <2>;
1399 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1403 clock-names = "baudclk", "apb_pclk";
1405 pinctrl-0 = <&uart8m0_xfer>;
1406 pinctrl-names = "default";
1407 reg-io-width = <4>;
1408 reg-shift = <2>;
1413 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1417 clock-names = "baudclk", "apb_pclk";
1419 pinctrl-0 = <&uart9m0_xfer>;
1420 pinctrl-names = "default";
1421 reg-io-width = <4>;
1422 reg-shift = <2>;
1426 thermal_zones: thermal-zones {
1427 cpu_thermal: cpu-thermal {
1428 polling-delay-passive = <100>;
1429 polling-delay = <1000>;
1431 thermal-sensors = <&tsadc 0>;
1451 cooling-maps {
1454 cooling-device =
1463 gpu_thermal: gpu-thermal {
1464 polling-delay-passive = <20>; /* milliseconds */
1465 polling-delay = <1000>; /* milliseconds */
1467 thermal-sensors = <&tsadc 1>;
1470 gpu_threshold: gpu-threshold {
1475 gpu_target: gpu-target {
1480 gpu_crit: gpu-crit {
1487 cooling-maps {
1490 cooling-device =
1498 compatible = "rockchip,rk3568-tsadc";
1501 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1502 assigned-clock-rates = <17000000>, <700000>;
1504 clock-names = "tsadc", "apb_pclk";
1507 rockchip,grf = <&grf>;
1508 rockchip,hw-tshut-temp = <95000>;
1509 pinctrl-names = "init", "default", "sleep";
1510 pinctrl-0 = <&tsadc_pin>;
1511 pinctrl-1 = <&tsadc_shutorg>;
1512 pinctrl-2 = <&tsadc_pin>;
1513 #thermal-sensor-cells = <1>;
1518 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1522 clock-names = "saradc", "apb_pclk";
1524 reset-names = "saradc-apb";
1525 #io-channel-cells = <1>;
1530 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1533 clock-names = "pwm", "pclk";
1534 pinctrl-0 = <&pwm4_pins>;
1535 pinctrl-names = "default";
1536 #pwm-cells = <3>;
1541 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1544 clock-names = "pwm", "pclk";
1545 pinctrl-0 = <&pwm5_pins>;
1546 pinctrl-names = "default";
1547 #pwm-cells = <3>;
1552 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1555 clock-names = "pwm", "pclk";
1556 pinctrl-0 = <&pwm6_pins>;
1557 pinctrl-names = "default";
1558 #pwm-cells = <3>;
1563 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1566 clock-names = "pwm", "pclk";
1567 pinctrl-0 = <&pwm7_pins>;
1568 pinctrl-names = "default";
1569 #pwm-cells = <3>;
1574 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1577 clock-names = "pwm", "pclk";
1578 pinctrl-0 = <&pwm8m0_pins>;
1579 pinctrl-names = "default";
1580 #pwm-cells = <3>;
1585 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1588 clock-names = "pwm", "pclk";
1589 pinctrl-0 = <&pwm9m0_pins>;
1590 pinctrl-names = "default";
1591 #pwm-cells = <3>;
1596 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1599 clock-names = "pwm", "pclk";
1600 pinctrl-0 = <&pwm10m0_pins>;
1601 pinctrl-names = "default";
1602 #pwm-cells = <3>;
1607 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1610 clock-names = "pwm", "pclk";
1611 pinctrl-0 = <&pwm11m0_pins>;
1612 pinctrl-names = "default";
1613 #pwm-cells = <3>;
1618 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1621 clock-names = "pwm", "pclk";
1622 pinctrl-0 = <&pwm12m0_pins>;
1623 pinctrl-names = "default";
1624 #pwm-cells = <3>;
1629 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1632 clock-names = "pwm", "pclk";
1633 pinctrl-0 = <&pwm13m0_pins>;
1634 pinctrl-names = "default";
1635 #pwm-cells = <3>;
1640 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1643 clock-names = "pwm", "pclk";
1644 pinctrl-0 = <&pwm14m0_pins>;
1645 pinctrl-names = "default";
1646 #pwm-cells = <3>;
1651 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1654 clock-names = "pwm", "pclk";
1655 pinctrl-0 = <&pwm15m0_pins>;
1656 pinctrl-names = "default";
1657 #pwm-cells = <3>;
1661 combphy1: phy@fe830000 {
1662 compatible = "rockchip,rk3568-naneng-combphy";
1667 clock-names = "ref", "apb", "pipe";
1668 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1669 assigned-clock-rates = <100000000>;
1671 rockchip,pipe-grf = <&pipegrf>;
1672 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1673 #phy-cells = <1>;
1677 combphy2: phy@fe840000 {
1678 compatible = "rockchip,rk3568-naneng-combphy";
1683 clock-names = "ref", "apb", "pipe";
1684 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1685 assigned-clock-rates = <100000000>;
1687 rockchip,pipe-grf = <&pipegrf>;
1688 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1689 #phy-cells = <1>;
1693 csi_dphy: phy@fe870000 {
1694 compatible = "rockchip,rk3568-csi-dphy";
1697 clock-names = "pclk";
1698 #phy-cells = <0>;
1700 reset-names = "apb";
1701 rockchip,grf = <&grf>;
1705 dsi_dphy0: mipi-dphy@fe850000 {
1706 compatible = "rockchip,rk3568-dsi-dphy";
1708 clock-names = "ref", "pclk";
1710 #phy-cells = <0>;
1711 power-domains = <&power RK3568_PD_VO>;
1712 reset-names = "apb";
1717 dsi_dphy1: mipi-dphy@fe860000 {
1718 compatible = "rockchip,rk3568-dsi-dphy";
1720 clock-names = "ref", "pclk";
1722 #phy-cells = <0>;
1723 power-domains = <&power RK3568_PD_VO>;
1724 reset-names = "apb";
1730 compatible = "rockchip,rk3568-usb2phy";
1733 clock-names = "phyclk";
1734 clock-output-names = "clk_usbphy0_480m";
1737 #clock-cells = <0>;
1740 usb2phy0_host: host-port {
1741 #phy-cells = <0>;
1745 usb2phy0_otg: otg-port {
1746 #phy-cells = <0>;
1752 compatible = "rockchip,rk3568-usb2phy";
1755 clock-names = "phyclk";
1756 clock-output-names = "clk_usbphy1_480m";
1759 #clock-cells = <0>;
1762 usb2phy1_host: host-port {
1763 #phy-cells = <0>;
1767 usb2phy1_otg: otg-port {
1768 #phy-cells = <0>;
1774 compatible = "rockchip,rk3568-pinctrl";
1775 rockchip,grf = <&grf>;
1777 #address-cells = <2>;
1778 #size-cells = <2>;
1782 compatible = "rockchip,gpio-bank";
1786 gpio-controller;
1787 #gpio-cells = <2>;
1788 interrupt-controller;
1789 #interrupt-cells = <2>;
1793 compatible = "rockchip,gpio-bank";
1797 gpio-controller;
1798 #gpio-cells = <2>;
1799 interrupt-controller;
1800 #interrupt-cells = <2>;
1804 compatible = "rockchip,gpio-bank";
1808 gpio-controller;
1809 #gpio-cells = <2>;
1810 interrupt-controller;
1811 #interrupt-cells = <2>;
1815 compatible = "rockchip,gpio-bank";
1819 gpio-controller;
1820 #gpio-cells = <2>;
1821 interrupt-controller;
1822 #interrupt-cells = <2>;
1826 compatible = "rockchip,gpio-bank";
1830 gpio-controller;
1831 #gpio-cells = <2>;
1832 interrupt-controller;
1833 #interrupt-cells = <2>;
1838 #include "rk3568-pinctrl.dtsi"