Lines Matching +full:0 +full:x0010f000
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
65 reg = <0x0 0x100>;
74 reg = <0x0 0x200>;
83 reg = <0x0 0x300>;
90 cpu0_opp_table: opp-table-0 {
140 arm,smc-id = <0x82000010>;
143 #size-cells = <0>;
146 reg = <0x14>;
229 #clock-cells = <0>;
236 pinctrl-0 = <&clk32k_out0>;
238 #clock-cells = <0>;
243 reg = <0x0 0x0010f000 0x0 0x100>;
246 ranges = <0 0x0 0x0010f000 0x100>;
248 scmi_shmem: sram@0 {
250 reg = <0x0 0x100>;
256 reg = <0 0xfc400000 0 0x1000>;
263 ports-implemented = <0x1>;
270 reg = <0 0xfc800000 0 0x1000>;
277 ports-implemented = <0x1>;
284 reg = <0x0 0xfcc00000 0x0 0x400000>;
300 reg = <0x0 0xfd000000 0x0 0x400000>;
318 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
319 <0x0 0xfd460000 0 0x80000>; /* GICR */
323 mbi-alias = <0x0 0xfd410000>;
330 reg = <0x0 0xfd800000 0x0 0x40000>;
341 reg = <0x0 0xfd840000 0x0 0x40000>;
352 reg = <0x0 0xfd880000 0x0 0x40000>;
363 reg = <0x0 0xfd8c0000 0x0 0x40000>;
374 reg = <0x0 0xfdc20000 0x0 0x10000>;
383 reg = <0x0 0xfdc50000 0x0 0x1000>;
388 reg = <0x0 0xfdc60000 0x0 0x10000>;
393 reg = <0x0 0xfdc80000 0x0 0x1000>;
398 reg = <0x0 0xfdc90000 0x0 0x1000>;
403 reg = <0x0 0xfdca0000 0x0 0x8000>;
408 reg = <0x0 0xfdca8000 0x0 0x8000>;
413 reg = <0x0 0xfdd00000 0x0 0x1000>;
420 reg = <0x0 0xfdd20000 0x0 0x1000>;
432 reg = <0x0 0xfdd40000 0x0 0x1000>;
436 pinctrl-0 = <&i2c0_xfer>;
439 #size-cells = <0>;
445 reg = <0x0 0xfdd50000 0x0 0x100>;
449 dmas = <&dmac0 0>, <&dmac0 1>;
450 pinctrl-0 = <&uart0_xfer>;
459 reg = <0x0 0xfdd70000 0x0 0x10>;
462 pinctrl-0 = <&pwm0m0_pins>;
470 reg = <0x0 0xfdd70010 0x0 0x10>;
473 pinctrl-0 = <&pwm1m0_pins>;
481 reg = <0x0 0xfdd70020 0x0 0x10>;
484 pinctrl-0 = <&pwm2m0_pins>;
492 reg = <0x0 0xfdd70030 0x0 0x10>;
495 pinctrl-0 = <&pwm3_pins>;
503 reg = <0x0 0xfdd90000 0x0 0x1000>;
509 #size-cells = <0>;
517 #power-domain-cells = <0>;
528 #power-domain-cells = <0>;
539 #power-domain-cells = <0>;
552 #power-domain-cells = <0>;
559 #power-domain-cells = <0>;
566 #power-domain-cells = <0>;
575 #power-domain-cells = <0>;
582 reg = <0x0 0xfde60000 0x0 0x4000>;
597 reg = <0x0 0xfdea0000 0x0 0x800>;
607 reg = <0x0 0xfdea0800 0x0 0x40>;
612 #iommu-cells = <0>;
617 reg = <0x0 0xfdee0000 0x0 0x800>;
627 reg = <0x0 0xfdee0800 0x0 0x40>;
632 #iommu-cells = <0>;
637 reg = <0x0 0xfe000000 0x0 0x4000>;
642 fifo-depth = <0x100>;
651 reg = <0x0 0xfe010000 0x0 0x10000>;
675 #address-cells = <0x1>;
676 #size-cells = <0x0>;
680 snps,blen = <0 0 0 0 16 8 4>;
697 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
710 #size-cells = <0>;
712 vp0: port@0 {
713 reg = <0>;
715 #size-cells = <0>;
721 #size-cells = <0>;
727 #size-cells = <0>;
734 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
738 #iommu-cells = <0>;
744 reg = <0x00 0xfe060000 0x00 0x10000>;
758 #size-cells = <0>;
760 dsi0_in: port@0 {
761 reg = <0>;
772 reg = <0x0 0xfe070000 0x0 0x10000>;
786 #size-cells = <0>;
788 dsi1_in: port@0 {
789 reg = <0>;
800 reg = <0x0 0xfe0a0000 0x0 0x20000>;
809 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
813 #sound-dai-cells = <0>;
818 #size-cells = <0>;
820 hdmi_in: port@0 {
821 reg = <0>;
832 reg = <0x0 0xfe128000 0x0 0x20>;
837 reg = <0x0 0xfe138080 0x0 0x20>;
842 reg = <0x0 0xfe138100 0x0 0x20>;
847 reg = <0x0 0xfe138180 0x0 0x20>;
852 reg = <0x0 0xfe148000 0x0 0x20>;
857 reg = <0x0 0xfe148080 0x0 0x20>;
862 reg = <0x0 0xfe148100 0x0 0x20>;
867 reg = <0x0 0xfe150000 0x0 0x20>;
872 reg = <0x0 0xfe158000 0x0 0x20>;
877 reg = <0x0 0xfe158100 0x0 0x20>;
882 reg = <0x0 0xfe158180 0x0 0x20>;
887 reg = <0x0 0xfe158200 0x0 0x20>;
892 reg = <0x0 0xfe158280 0x0 0x20>;
897 reg = <0x0 0xfe158300 0x0 0x20>;
902 reg = <0x0 0xfe180000 0x0 0x20>;
907 reg = <0x0 0xfe190000 0x0 0x20>;
912 reg = <0x0 0xfe190280 0x0 0x20>;
917 reg = <0x0 0xfe190300 0x0 0x20>;
922 reg = <0x0 0xfe190380 0x0 0x20>;
927 reg = <0x0 0xfe190400 0x0 0x20>;
932 reg = <0x0 0xfe198000 0x0 0x20>;
937 reg = <0x0 0xfe1a8000 0x0 0x20>;
942 reg = <0x0 0xfe1a8080 0x0 0x20>;
947 reg = <0x0 0xfe1a8100 0x0 0x20>;
952 reg = <0x3 0xc0000000 0x0 0x00400000>,
953 <0x0 0xfe260000 0x0 0x00010000>,
954 <0x3 0x3f000000 0x0 0x01000000>;
962 bus-range = <0x0 0xf>;
969 interrupt-map-mask = <0 0 0 7>;
970 interrupt-map = <0 0 0 1 &pcie_intc 0>,
971 <0 0 0 2 &pcie_intc 1>,
972 <0 0 0 3 &pcie_intc 2>,
973 <0 0 0 4 &pcie_intc 3>;
974 linux,pci-domain = <0>;
978 msi-map = <0x0 &gic 0x0 0x1000>;
983 ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
984 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
992 #address-cells = <0>;
1002 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1007 fifo-depth = <0x100>;
1016 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1021 fifo-depth = <0x100>;
1030 reg = <0x0 0xfe300000 0x0 0x4000>;
1034 pinctrl-0 = <&fspi_pins>;
1041 reg = <0x0 0xfe310000 0x0 0x10000>;
1054 reg = <0x0 0xfe460000 0x0 0x1000>;
1061 pinctrl-0 = <&spdifm0_tx>;
1062 #sound-dai-cells = <0>;
1068 reg = <0x0 0xfe400000 0x0 0x1000>;
1074 dmas = <&dmac1 0>;
1079 #sound-dai-cells = <0>;
1085 reg = <0x0 0xfe410000 0x0 0x1000>;
1098 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1104 #sound-dai-cells = <0>;
1110 reg = <0x0 0xfe430000 0x0 0x1000>;
1120 #sound-dai-cells = <0>;
1126 reg = <0x0 0xfe440000 0x0 0x1000>;
1132 pinctrl-0 = <&pdmm0_clk
1141 #sound-dai-cells = <0>;
1147 reg = <0x0 0xfe530000 0x0 0x4000>;
1158 reg = <0x0 0xfe550000 0x0 0x4000>;
1169 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1173 pinctrl-0 = <&i2c1_xfer>;
1176 #size-cells = <0>;
1182 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1186 pinctrl-0 = <&i2c2m0_xfer>;
1189 #size-cells = <0>;
1195 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1199 pinctrl-0 = <&i2c3m0_xfer>;
1202 #size-cells = <0>;
1208 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1212 pinctrl-0 = <&i2c4m0_xfer>;
1215 #size-cells = <0>;
1221 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1225 pinctrl-0 = <&i2c5m0_xfer>;
1228 #size-cells = <0>;
1234 reg = <0x0 0xfe600000 0x0 0x100>;
1242 reg = <0x0 0xfe610000 0x0 0x1000>;
1249 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1251 #size-cells = <0>;
1257 reg = <0x0 0xfe620000 0x0 0x1000>;
1264 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1266 #size-cells = <0>;
1272 reg = <0x0 0xfe630000 0x0 0x1000>;
1279 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1281 #size-cells = <0>;
1287 reg = <0x0 0xfe640000 0x0 0x1000>;
1294 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1296 #size-cells = <0>;
1302 reg = <0x0 0xfe650000 0x0 0x100>;
1307 pinctrl-0 = <&uart1m0_xfer>;
1316 reg = <0x0 0xfe660000 0x0 0x100>;
1321 pinctrl-0 = <&uart2m0_xfer>;
1330 reg = <0x0 0xfe670000 0x0 0x100>;
1335 pinctrl-0 = <&uart3m0_xfer>;
1344 reg = <0x0 0xfe680000 0x0 0x100>;
1349 pinctrl-0 = <&uart4m0_xfer>;
1358 reg = <0x0 0xfe690000 0x0 0x100>;
1363 pinctrl-0 = <&uart5m0_xfer>;
1372 reg = <0x0 0xfe6a0000 0x0 0x100>;
1377 pinctrl-0 = <&uart6m0_xfer>;
1386 reg = <0x0 0xfe6b0000 0x0 0x100>;
1391 pinctrl-0 = <&uart7m0_xfer>;
1400 reg = <0x0 0xfe6c0000 0x0 0x100>;
1405 pinctrl-0 = <&uart8m0_xfer>;
1414 reg = <0x0 0xfe6d0000 0x0 0x100>;
1419 pinctrl-0 = <&uart9m0_xfer>;
1431 thermal-sensors = <&tsadc 0>;
1499 reg = <0x0 0xfe710000 0x0 0x100>;
1510 pinctrl-0 = <&tsadc_pin>;
1519 reg = <0x0 0xfe720000 0x0 0x100>;
1531 reg = <0x0 0xfe6e0000 0x0 0x10>;
1534 pinctrl-0 = <&pwm4_pins>;
1542 reg = <0x0 0xfe6e0010 0x0 0x10>;
1545 pinctrl-0 = <&pwm5_pins>;
1553 reg = <0x0 0xfe6e0020 0x0 0x10>;
1556 pinctrl-0 = <&pwm6_pins>;
1564 reg = <0x0 0xfe6e0030 0x0 0x10>;
1567 pinctrl-0 = <&pwm7_pins>;
1575 reg = <0x0 0xfe6f0000 0x0 0x10>;
1578 pinctrl-0 = <&pwm8m0_pins>;
1586 reg = <0x0 0xfe6f0010 0x0 0x10>;
1589 pinctrl-0 = <&pwm9m0_pins>;
1597 reg = <0x0 0xfe6f0020 0x0 0x10>;
1600 pinctrl-0 = <&pwm10m0_pins>;
1608 reg = <0x0 0xfe6f0030 0x0 0x10>;
1611 pinctrl-0 = <&pwm11m0_pins>;
1619 reg = <0x0 0xfe700000 0x0 0x10>;
1622 pinctrl-0 = <&pwm12m0_pins>;
1630 reg = <0x0 0xfe700010 0x0 0x10>;
1633 pinctrl-0 = <&pwm13m0_pins>;
1641 reg = <0x0 0xfe700020 0x0 0x10>;
1644 pinctrl-0 = <&pwm14m0_pins>;
1652 reg = <0x0 0xfe700030 0x0 0x10>;
1655 pinctrl-0 = <&pwm15m0_pins>;
1663 reg = <0x0 0xfe830000 0x0 0x100>;
1679 reg = <0x0 0xfe840000 0x0 0x100>;
1695 reg = <0x0 0xfe870000 0x0 0x10000>;
1698 #phy-cells = <0>;
1707 reg = <0x0 0xfe850000 0x0 0x10000>;
1710 #phy-cells = <0>;
1719 reg = <0x0 0xfe860000 0x0 0x10000>;
1722 #phy-cells = <0>;
1731 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1737 #clock-cells = <0>;
1741 #phy-cells = <0>;
1746 #phy-cells = <0>;
1753 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1759 #clock-cells = <0>;
1763 #phy-cells = <0>;
1768 #phy-cells = <0>;
1783 reg = <0x0 0xfdd60000 0x0 0x100>;
1794 reg = <0x0 0xfe740000 0x0 0x100>;
1805 reg = <0x0 0xfe750000 0x0 0x100>;
1816 reg = <0x0 0xfe760000 0x0 0x100>;
1827 reg = <0x0 0xfe770000 0x0 0x100>;