Lines Matching +full:0 +full:xfe8c0000
13 reg = <0 0xfc000000 0 0x1000>;
20 ports-implemented = <0x1>;
27 reg = <0x0 0xfdc70000 0x0 0x1000>;
32 reg = <0x0 0xfe190080 0x0 0x20>;
37 reg = <0x0 0xfe190100 0x0 0x20>;
42 reg = <0x0 0xfe190200 0x0 0x20>;
47 reg = <0x0 0xfdcb8000 0x0 0x10000>;
52 reg = <0x0 0xfe8c0000 0x0 0x20000>;
53 #phy-cells = <0>;
67 bus-range = <0x0 0xf>;
81 interrupt-map-mask = <0 0 0 7>;
82 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
83 <0 0 0 2 &pcie3x1_intc 1>,
84 <0 0 0 3 &pcie3x1_intc 2>,
85 <0 0 0 4 &pcie3x1_intc 3>;
90 msi-map = <0x0 &gic 0x1000 0x1000>;
95 reg = <0x3 0xc0400000 0x0 0x00400000>,
96 <0x0 0xfe270000 0x0 0x00010000>,
97 <0x3 0x7f000000 0x0 0x01000000>;
98 ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
99 <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
108 #address-cells = <0>;
119 bus-range = <0x0 0xf>;
133 interrupt-map-mask = <0 0 0 7>;
134 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
135 <0 0 0 2 &pcie3x2_intc 1>,
136 <0 0 0 3 &pcie3x2_intc 2>,
137 <0 0 0 4 &pcie3x2_intc 3>;
142 msi-map = <0x0 &gic 0x2000 0x1000>;
147 reg = <0x3 0xc0800000 0x0 0x00400000>,
148 <0x0 0xfe280000 0x0 0x00010000>,
149 <0x3 0xbf000000 0x0 0x01000000>;
150 ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
151 <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
160 #address-cells = <0>;
169 reg = <0x0 0xfe2a0000 0x0 0x10000>;
193 #address-cells = <0x1>;
194 #size-cells = <0x0>;
198 snps,blen = <0 0 0 0 16 8 4>;
216 reg = <0x0 0xfe820000 0x0 0x100>;
254 #power-domain-cells = <0>;