Lines Matching +full:bus +full:- +full:dmc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
40 #address-cells = <2>;
41 #size-cells = <0>;
43 cpu-map {
71 compatible = "arm,cortex-a53";
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
119 compatible = "arm,cortex-a72";
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
128 thermal-idle {
129 #cooling-cells = <2>;
130 duration-us = <10000>;
131 exit-latency-us = <500>;
137 compatible = "arm,cortex-a72";
139 enable-method = "psci";
140 capacity-dmips-mhz = <1024>;
142 #cooling-cells = <2>; /* min followed by max */
143 dynamic-power-coefficient = <436>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
146 thermal-idle {
147 #cooling-cells = <2>;
148 duration-us = <10000>;
149 exit-latency-us = <500>;
153 idle-states {
154 entry-method = "psci";
156 CPU_SLEEP: cpu-sleep {
157 compatible = "arm,idle-state";
158 local-timer-stop;
159 arm,psci-suspend-param = <0x0010000>;
160 entry-latency-us = <120>;
161 exit-latency-us = <250>;
162 min-residency-us = <900>;
165 CLUSTER_SLEEP: cluster-sleep {
166 compatible = "arm,idle-state";
167 local-timer-stop;
168 arm,psci-suspend-param = <0x1010000>;
169 entry-latency-us = <400>;
170 exit-latency-us = <500>;
171 min-residency-us = <2000>;
176 display-subsystem {
177 compatible = "rockchip,display-subsystem";
181 dmc: memory-controller { label
182 compatible = "rockchip,rk3399-dmc";
184 devfreq-events = <&dfi>;
186 clock-names = "dmc_clk";
191 compatible = "arm,cortex-a53-pmu";
196 compatible = "arm,cortex-a72-pmu";
201 compatible = "arm,psci-1.0";
206 compatible = "arm,armv8-timer";
211 arm,no-tick-in-suspend;
215 compatible = "fixed-clock";
216 clock-frequency = <24000000>;
217 clock-output-names = "xin24m";
218 #clock-cells = <0>;
222 compatible = "rockchip,rk3399-pcie";
225 reg-names = "axi-base", "apb-base";
227 #address-cells = <3>;
228 #size-cells = <2>;
229 #interrupt-cells = <1>;
230 aspm-no-l0s;
231 bus-range = <0x0 0x1f>;
234 clock-names = "aclk", "aclk-perf",
239 interrupt-names = "sys", "legacy", "client";
240 interrupt-map-mask = <0 0 0 7>;
241 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
245 max-link-speed = <1>;
246 msi-map = <0x0 &its 0x0 0x1000>;
249 phy-names = "pcie-phy-0", "pcie-phy-1",
250 "pcie-phy-2", "pcie-phy-3";
257 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
261 pcie0_intc: interrupt-controller {
262 interrupt-controller;
263 #address-cells = <0>;
264 #interrupt-cells = <1>;
269 compatible = "rockchip,rk3399-gmac";
272 interrupt-names = "macirq";
277 clock-names = "stmmaceth", "mac_clk_rx",
281 power-domains = <&power RK3399_PD_GMAC>;
283 reset-names = "stmmaceth";
290 compatible = "rockchip,rk3399-dw-mshc",
291 "rockchip,rk3288-dw-mshc";
294 max-frequency = <150000000>;
297 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
298 fifo-depth = <0x100>;
299 power-domains = <&power RK3399_PD_SDIOAUDIO>;
301 reset-names = "reset";
306 compatible = "rockchip,rk3399-dw-mshc",
307 "rockchip,rk3288-dw-mshc";
310 max-frequency = <150000000>;
311 assigned-clocks = <&cru HCLK_SD>;
312 assigned-clock-rates = <200000000>;
315 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
316 fifo-depth = <0x100>;
317 power-domains = <&power RK3399_PD_SD>;
319 reset-names = "reset";
324 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
327 arasan,soc-ctl-syscon = <&grf>;
328 assigned-clocks = <&cru SCLK_EMMC>;
329 assigned-clock-rates = <200000000>;
331 clock-names = "clk_xin", "clk_ahb";
332 clock-output-names = "emmc_cardclock";
333 #clock-cells = <0>;
335 phy-names = "phy_arasan";
336 power-domains = <&power RK3399_PD_EMMC>;
337 disable-cqe-dcmd;
342 compatible = "generic-ehci";
348 phy-names = "usb";
353 compatible = "generic-ohci";
359 phy-names = "usb";
364 compatible = "generic-ehci";
370 phy-names = "usb";
375 compatible = "generic-ohci";
381 phy-names = "usb";
386 compatible = "arm,coresight-cpu-debug", "arm,primecell";
389 clock-names = "apb_pclk";
394 compatible = "arm,coresight-cpu-debug", "arm,primecell";
397 clock-names = "apb_pclk";
402 compatible = "arm,coresight-cpu-debug", "arm,primecell";
405 clock-names = "apb_pclk";
410 compatible = "arm,coresight-cpu-debug", "arm,primecell";
413 clock-names = "apb_pclk";
418 compatible = "arm,coresight-cpu-debug", "arm,primecell";
421 clock-names = "apb_pclk";
426 compatible = "arm,coresight-cpu-debug", "arm,primecell";
429 clock-names = "apb_pclk";
434 compatible = "rockchip,rk3399-dwc3";
435 #address-cells = <2>;
436 #size-cells = <2>;
441 clock-names = "ref_clk", "suspend_clk",
445 reset-names = "usb3-otg";
454 clock-names = "ref", "bus_early", "suspend";
457 phy-names = "usb2-phy", "usb3-phy";
460 snps,dis-u2-freeclk-exists-quirk;
462 snps,dis-del-phy-power-chg-quirk;
463 snps,dis-tx-ipgap-linecheck-quirk;
464 power-domains = <&power RK3399_PD_USB3>;
470 compatible = "rockchip,rk3399-dwc3";
471 #address-cells = <2>;
472 #size-cells = <2>;
477 clock-names = "ref_clk", "suspend_clk",
481 reset-names = "usb3-otg";
490 clock-names = "ref", "bus_early", "suspend";
493 phy-names = "usb2-phy", "usb3-phy";
496 snps,dis-u2-freeclk-exists-quirk;
498 snps,dis-del-phy-power-chg-quirk;
499 snps,dis-tx-ipgap-linecheck-quirk;
500 power-domains = <&power RK3399_PD_USB3>;
506 compatible = "rockchip,rk3399-cdn-dp";
509 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
510 assigned-clock-rates = <100000000>, <200000000>;
513 clock-names = "core-clk", "pclk", "spdif", "grf";
515 power-domains = <&power RK3399_PD_HDCP>;
518 reset-names = "spdif", "dptx", "apb", "core";
520 #sound-dai-cells = <1>;
525 #address-cells = <1>;
526 #size-cells = <0>;
530 remote-endpoint = <&vopb_out_dp>;
535 remote-endpoint = <&vopl_out_dp>;
541 gic: interrupt-controller@fee00000 {
542 compatible = "arm,gic-v3";
543 #interrupt-cells = <4>;
544 #address-cells = <2>;
545 #size-cells = <2>;
547 interrupt-controller;
555 its: interrupt-controller@fee20000 {
556 compatible = "arm,gic-v3-its";
557 msi-controller;
558 #msi-cells = <1>;
562 ppi-partitions {
563 ppi_cluster0: interrupt-partition-0 {
567 ppi_cluster1: interrupt-partition-1 {
574 compatible = "rockchip,rk3399-saradc";
577 #io-channel-cells = <1>;
579 clock-names = "saradc", "apb_pclk";
581 reset-names = "saradc-apb";
586 compatible = "rockchip,rk3399-i2c";
588 assigned-clocks = <&cru SCLK_I2C1>;
589 assigned-clock-rates = <200000000>;
591 clock-names = "i2c", "pclk";
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>;
596 #size-cells = <0>;
601 compatible = "rockchip,rk3399-i2c";
603 assigned-clocks = <&cru SCLK_I2C2>;
604 assigned-clock-rates = <200000000>;
606 clock-names = "i2c", "pclk";
608 pinctrl-names = "default";
609 pinctrl-0 = <&i2c2_xfer>;
610 #address-cells = <1>;
611 #size-cells = <0>;
616 compatible = "rockchip,rk3399-i2c";
618 assigned-clocks = <&cru SCLK_I2C3>;
619 assigned-clock-rates = <200000000>;
621 clock-names = "i2c", "pclk";
623 pinctrl-names = "default";
624 pinctrl-0 = <&i2c3_xfer>;
625 #address-cells = <1>;
626 #size-cells = <0>;
631 compatible = "rockchip,rk3399-i2c";
633 assigned-clocks = <&cru SCLK_I2C5>;
634 assigned-clock-rates = <200000000>;
636 clock-names = "i2c", "pclk";
638 pinctrl-names = "default";
639 pinctrl-0 = <&i2c5_xfer>;
640 #address-cells = <1>;
641 #size-cells = <0>;
646 compatible = "rockchip,rk3399-i2c";
648 assigned-clocks = <&cru SCLK_I2C6>;
649 assigned-clock-rates = <200000000>;
651 clock-names = "i2c", "pclk";
653 pinctrl-names = "default";
654 pinctrl-0 = <&i2c6_xfer>;
655 #address-cells = <1>;
656 #size-cells = <0>;
661 compatible = "rockchip,rk3399-i2c";
663 assigned-clocks = <&cru SCLK_I2C7>;
664 assigned-clock-rates = <200000000>;
666 clock-names = "i2c", "pclk";
668 pinctrl-names = "default";
669 pinctrl-0 = <&i2c7_xfer>;
670 #address-cells = <1>;
671 #size-cells = <0>;
676 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
679 clock-names = "baudclk", "apb_pclk";
681 reg-shift = <2>;
682 reg-io-width = <4>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&uart0_xfer>;
689 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
692 clock-names = "baudclk", "apb_pclk";
694 reg-shift = <2>;
695 reg-io-width = <4>;
696 pinctrl-names = "default";
697 pinctrl-0 = <&uart1_xfer>;
702 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
705 clock-names = "baudclk", "apb_pclk";
707 reg-shift = <2>;
708 reg-io-width = <4>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&uart2c_xfer>;
715 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
718 clock-names = "baudclk", "apb_pclk";
720 reg-shift = <2>;
721 reg-io-width = <4>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&uart3_xfer>;
728 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
731 clock-names = "spiclk", "apb_pclk";
734 dma-names = "tx", "rx";
735 pinctrl-names = "default";
736 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
737 #address-cells = <1>;
738 #size-cells = <0>;
743 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
746 clock-names = "spiclk", "apb_pclk";
749 dma-names = "tx", "rx";
750 pinctrl-names = "default";
751 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
752 #address-cells = <1>;
753 #size-cells = <0>;
758 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
761 clock-names = "spiclk", "apb_pclk";
764 dma-names = "tx", "rx";
765 pinctrl-names = "default";
766 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
767 #address-cells = <1>;
768 #size-cells = <0>;
773 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
776 clock-names = "spiclk", "apb_pclk";
779 dma-names = "tx", "rx";
780 pinctrl-names = "default";
781 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
782 #address-cells = <1>;
783 #size-cells = <0>;
788 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
791 clock-names = "spiclk", "apb_pclk";
794 dma-names = "tx", "rx";
795 pinctrl-names = "default";
796 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
797 power-domains = <&power RK3399_PD_SDIOAUDIO>;
798 #address-cells = <1>;
799 #size-cells = <0>;
803 thermal_zones: thermal-zones {
804 cpu_thermal: cpu-thermal {
805 polling-delay-passive = <100>;
806 polling-delay = <1000>;
808 thermal-sensors = <&tsadc 0>;
828 cooling-maps {
831 cooling-device =
837 cooling-device =
848 gpu_thermal: gpu-thermal {
849 polling-delay-passive = <100>;
850 polling-delay = <1000>;
852 thermal-sensors = <&tsadc 1>;
867 cooling-maps {
870 cooling-device =
878 compatible = "rockchip,rk3399-tsadc";
881 assigned-clocks = <&cru SCLK_TSADC>;
882 assigned-clock-rates = <750000>;
884 clock-names = "tsadc", "apb_pclk";
886 reset-names = "tsadc-apb";
888 rockchip,hw-tshut-temp = <95000>;
889 pinctrl-names = "init", "default", "sleep";
890 pinctrl-0 = <&otp_pin>;
891 pinctrl-1 = <&otp_out>;
892 pinctrl-2 = <&otp_pin>;
893 #thermal-sensor-cells = <1>;
898 compatible = "rockchip,rk3399-qos", "syscon";
903 compatible = "rockchip,rk3399-qos", "syscon";
908 compatible = "rockchip,rk3399-qos", "syscon";
913 compatible = "rockchip,rk3399-qos", "syscon";
918 compatible = "rockchip,rk3399-qos", "syscon";
923 compatible = "rockchip,rk3399-qos", "syscon";
928 compatible = "rockchip,rk3399-qos", "syscon";
933 compatible = "rockchip,rk3399-qos", "syscon";
938 compatible = "rockchip,rk3399-qos", "syscon";
943 compatible = "rockchip,rk3399-qos", "syscon";
948 compatible = "rockchip,rk3399-qos", "syscon";
953 compatible = "rockchip,rk3399-qos", "syscon";
958 compatible = "rockchip,rk3399-qos", "syscon";
963 compatible = "rockchip,rk3399-qos", "syscon";
968 compatible = "rockchip,rk3399-qos", "syscon";
973 compatible = "rockchip,rk3399-qos", "syscon";
978 compatible = "rockchip,rk3399-qos", "syscon";
983 compatible = "rockchip,rk3399-qos", "syscon";
988 compatible = "rockchip,rk3399-qos", "syscon";
993 compatible = "rockchip,rk3399-qos", "syscon";
998 compatible = "rockchip,rk3399-qos", "syscon";
1003 compatible = "rockchip,rk3399-qos", "syscon";
1008 compatible = "rockchip,rk3399-qos", "syscon";
1013 compatible = "rockchip,rk3399-qos", "syscon";
1018 compatible = "rockchip,rk3399-qos", "syscon";
1022 pmu: power-management@ff310000 {
1023 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1033 power: power-controller {
1034 compatible = "rockchip,rk3399-power-controller";
1035 #power-domain-cells = <1>;
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1040 power-domain@RK3399_PD_IEP {
1045 #power-domain-cells = <0>;
1047 power-domain@RK3399_PD_RGA {
1053 #power-domain-cells = <0>;
1055 power-domain@RK3399_PD_VCODEC {
1060 #power-domain-cells = <0>;
1062 power-domain@RK3399_PD_VDU {
1068 #power-domain-cells = <0>;
1072 power-domain@RK3399_PD_GPU {
1076 #power-domain-cells = <0>;
1080 power-domain@RK3399_PD_EDP {
1083 #power-domain-cells = <0>;
1085 power-domain@RK3399_PD_EMMC {
1089 #power-domain-cells = <0>;
1091 power-domain@RK3399_PD_GMAC {
1096 #power-domain-cells = <0>;
1098 power-domain@RK3399_PD_SD {
1103 #power-domain-cells = <0>;
1105 power-domain@RK3399_PD_SDIOAUDIO {
1109 #power-domain-cells = <0>;
1111 power-domain@RK3399_PD_TCPD0 {
1115 #power-domain-cells = <0>;
1117 power-domain@RK3399_PD_TCPD1 {
1121 #power-domain-cells = <0>;
1123 power-domain@RK3399_PD_USB3 {
1128 #power-domain-cells = <0>;
1130 power-domain@RK3399_PD_VIO {
1132 #power-domain-cells = <1>;
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1136 power-domain@RK3399_PD_HDCP {
1142 #power-domain-cells = <0>;
1144 power-domain@RK3399_PD_ISP0 {
1150 #power-domain-cells = <0>;
1152 power-domain@RK3399_PD_ISP1 {
1158 #power-domain-cells = <0>;
1160 power-domain@RK3399_PD_VO {
1162 #power-domain-cells = <1>;
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1166 power-domain@RK3399_PD_VOPB {
1172 #power-domain-cells = <0>;
1174 power-domain@RK3399_PD_VOPL {
1179 #power-domain-cells = <0>;
1187 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1190 pmu_io_domains: io-domains {
1191 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1197 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1200 clock-names = "spiclk", "apb_pclk";
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1210 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1213 clock-names = "baudclk", "apb_pclk";
1215 reg-shift = <2>;
1216 reg-io-width = <4>;
1217 pinctrl-names = "default";
1218 pinctrl-0 = <&uart4_xfer>;
1223 compatible = "rockchip,rk3399-i2c";
1225 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1226 assigned-clock-rates = <200000000>;
1228 clock-names = "i2c", "pclk";
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&i2c0_xfer>;
1232 #address-cells = <1>;
1233 #size-cells = <0>;
1238 compatible = "rockchip,rk3399-i2c";
1240 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1241 assigned-clock-rates = <200000000>;
1243 clock-names = "i2c", "pclk";
1245 pinctrl-names = "default";
1246 pinctrl-0 = <&i2c4_xfer>;
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1253 compatible = "rockchip,rk3399-i2c";
1255 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1256 assigned-clock-rates = <200000000>;
1258 clock-names = "i2c", "pclk";
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&i2c8_xfer>;
1262 #address-cells = <1>;
1263 #size-cells = <0>;
1268 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1270 #pwm-cells = <3>;
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&pwm0_pin>;
1278 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1280 #pwm-cells = <3>;
1281 pinctrl-names = "default";
1282 pinctrl-0 = <&pwm1_pin>;
1288 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1290 #pwm-cells = <3>;
1291 pinctrl-names = "default";
1292 pinctrl-0 = <&pwm2_pin>;
1298 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1300 #pwm-cells = <3>;
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&pwm3a_pin>;
1309 compatible = "rockchip,rk3399-dfi";
1313 clock-names = "pclk_ddr_mon";
1317 vpu: video-codec@ff650000 {
1318 compatible = "rockchip,rk3399-vpu";
1322 interrupt-names = "vepu", "vdpu";
1324 clock-names = "aclk", "hclk";
1326 power-domains = <&power RK3399_PD_VCODEC>;
1334 clock-names = "aclk", "iface";
1335 #iommu-cells = <0>;
1336 power-domains = <&power RK3399_PD_VCODEC>;
1339 vdec: video-codec@ff660000 {
1340 compatible = "rockchip,rk3399-vdec";
1345 clock-names = "axi", "ahb", "cabac", "core";
1347 power-domains = <&power RK3399_PD_VDU>;
1355 clock-names = "aclk", "iface";
1356 power-domains = <&power RK3399_PD_VDU>;
1357 #iommu-cells = <0>;
1365 clock-names = "aclk", "iface";
1366 #iommu-cells = <0>;
1371 compatible = "rockchip,rk3399-rga";
1375 clock-names = "aclk", "hclk", "sclk";
1377 reset-names = "core", "axi", "ahb";
1378 power-domains = <&power RK3399_PD_RGA>;
1382 compatible = "rockchip,rk3399-efuse";
1384 #address-cells = <1>;
1385 #size-cells = <1>;
1387 clock-names = "pclk_efuse";
1390 cpu_id: cpu-id@7 {
1393 cpub_leakage: cpu-leakage@17 {
1396 gpu_leakage: gpu-leakage@18 {
1399 center_leakage: center-leakage@19 {
1402 cpul_leakage: cpu-leakage@1a {
1405 logic_leakage: logic-leakage@1b {
1408 wafer_info: wafer-info@1c {
1413 dmac_bus: dma-controller@ff6d0000 {
1418 #dma-cells = <1>;
1419 arm,pl330-periph-burst;
1421 clock-names = "apb_pclk";
1424 dmac_peri: dma-controller@ff6e0000 {
1429 #dma-cells = <1>;
1430 arm,pl330-periph-burst;
1432 clock-names = "apb_pclk";
1435 pmucru: clock-controller@ff750000 {
1436 compatible = "rockchip,rk3399-pmucru";
1439 clock-names = "xin24m";
1441 #clock-cells = <1>;
1442 #reset-cells = <1>;
1443 assigned-clocks = <&pmucru PLL_PPLL>;
1444 assigned-clock-rates = <676000000>;
1447 cru: clock-controller@ff760000 {
1448 compatible = "rockchip,rk3399-cru";
1451 clock-names = "xin24m";
1453 #clock-cells = <1>;
1454 #reset-cells = <1>;
1455 assigned-clocks =
1467 assigned-clock-rates =
1482 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1484 #address-cells = <1>;
1485 #size-cells = <1>;
1487 io_domains: io-domains {
1488 compatible = "rockchip,rk3399-io-voltage-domain";
1492 mipi_dphy_rx0: mipi-dphy-rx0 {
1493 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1497 clock-names = "dphy-ref", "dphy-cfg", "grf";
1498 power-domains = <&power RK3399_PD_VIO>;
1499 #phy-cells = <0>;
1504 compatible = "rockchip,rk3399-usb2phy";
1507 clock-names = "phyclk";
1508 #clock-cells = <0>;
1509 clock-output-names = "clk_usbphy0_480m";
1512 u2phy0_host: host-port {
1513 #phy-cells = <0>;
1515 interrupt-names = "linestate";
1519 u2phy0_otg: otg-port {
1520 #phy-cells = <0>;
1524 interrupt-names = "otg-bvalid", "otg-id",
1531 compatible = "rockchip,rk3399-usb2phy";
1534 clock-names = "phyclk";
1535 #clock-cells = <0>;
1536 clock-output-names = "clk_usbphy1_480m";
1539 u2phy1_host: host-port {
1540 #phy-cells = <0>;
1542 interrupt-names = "linestate";
1546 u2phy1_otg: otg-port {
1547 #phy-cells = <0>;
1551 interrupt-names = "otg-bvalid", "otg-id",
1558 compatible = "rockchip,rk3399-emmc-phy";
1561 clock-names = "emmcclk";
1562 drive-impedance-ohm = <50>;
1563 #phy-cells = <0>;
1567 pcie_phy: pcie-phy {
1568 compatible = "rockchip,rk3399-pcie-phy";
1570 clock-names = "refclk";
1571 #phy-cells = <1>;
1573 reset-names = "phy";
1579 compatible = "rockchip,rk3399-typec-phy";
1583 clock-names = "tcpdcore", "tcpdphy-ref";
1584 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1585 assigned-clock-rates = <50000000>;
1586 power-domains = <&power RK3399_PD_TCPD0>;
1590 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1594 tcphy0_dp: dp-port {
1595 #phy-cells = <0>;
1598 tcphy0_usb3: usb3-port {
1599 #phy-cells = <0>;
1604 compatible = "rockchip,rk3399-typec-phy";
1608 clock-names = "tcpdcore", "tcpdphy-ref";
1609 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1610 assigned-clock-rates = <50000000>;
1611 power-domains = <&power RK3399_PD_TCPD1>;
1615 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1619 tcphy1_dp: dp-port {
1620 #phy-cells = <0>;
1623 tcphy1_usb3: usb3-port {
1624 #phy-cells = <0>;
1629 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1636 compatible = "rockchip,rk3399-timer";
1640 clock-names = "pclk", "timer";
1644 compatible = "rockchip,rk3399-spdif";
1648 dma-names = "tx";
1649 clock-names = "mclk", "hclk";
1651 pinctrl-names = "default";
1652 pinctrl-0 = <&spdif_bus>;
1653 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1654 #sound-dai-cells = <0>;
1659 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1664 dma-names = "tx", "rx";
1665 clock-names = "i2s_clk", "i2s_hclk";
1667 pinctrl-names = "bclk_on", "bclk_off";
1668 pinctrl-0 = <&i2s0_8ch_bus>;
1669 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
1670 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1671 #sound-dai-cells = <0>;
1676 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1680 dma-names = "tx", "rx";
1681 clock-names = "i2s_clk", "i2s_hclk";
1683 pinctrl-names = "default";
1684 pinctrl-0 = <&i2s1_2ch_bus>;
1685 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1686 #sound-dai-cells = <0>;
1691 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1695 dma-names = "tx", "rx";
1696 clock-names = "i2s_clk", "i2s_hclk";
1698 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1699 #sound-dai-cells = <0>;
1704 compatible = "rockchip,rk3399-vop-lit";
1707 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1708 assigned-clock-rates = <400000000>, <100000000>;
1710 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1712 power-domains = <&power RK3399_PD_VOPL>;
1714 reset-names = "axi", "ahb", "dclk";
1718 #address-cells = <1>;
1719 #size-cells = <0>;
1723 remote-endpoint = <&mipi_in_vopl>;
1728 remote-endpoint = <&edp_in_vopl>;
1733 remote-endpoint = <&hdmi_in_vopl>;
1738 remote-endpoint = <&mipi1_in_vopl>;
1743 remote-endpoint = <&dp_in_vopl>;
1753 clock-names = "aclk", "iface";
1754 power-domains = <&power RK3399_PD_VOPL>;
1755 #iommu-cells = <0>;
1760 compatible = "rockchip,rk3399-vop-big";
1763 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1764 assigned-clock-rates = <400000000>, <100000000>;
1766 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1768 power-domains = <&power RK3399_PD_VOPB>;
1770 reset-names = "axi", "ahb", "dclk";
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1779 remote-endpoint = <&edp_in_vopb>;
1784 remote-endpoint = <&mipi_in_vopb>;
1789 remote-endpoint = <&hdmi_in_vopb>;
1794 remote-endpoint = <&mipi1_in_vopb>;
1799 remote-endpoint = <&dp_in_vopb>;
1809 clock-names = "aclk", "iface";
1810 power-domains = <&power RK3399_PD_VOPB>;
1811 #iommu-cells = <0>;
1816 compatible = "rockchip,rk3399-cif-isp";
1822 clock-names = "isp", "aclk", "hclk";
1825 phy-names = "dphy";
1826 power-domains = <&power RK3399_PD_ISP0>;
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1835 #address-cells = <1>;
1836 #size-cells = <0>;
1846 clock-names = "aclk", "iface";
1847 #iommu-cells = <0>;
1848 power-domains = <&power RK3399_PD_ISP0>;
1849 rockchip,disable-mmu-reset;
1853 compatible = "rockchip,rk3399-cif-isp";
1859 clock-names = "isp", "aclk", "hclk";
1862 phy-names = "dphy";
1863 power-domains = <&power RK3399_PD_ISP1>;
1867 #address-cells = <1>;
1868 #size-cells = <0>;
1872 #address-cells = <1>;
1873 #size-cells = <0>;
1883 clock-names = "aclk", "iface";
1884 #iommu-cells = <0>;
1885 power-domains = <&power RK3399_PD_ISP1>;
1886 rockchip,disable-mmu-reset;
1889 hdmi_sound: hdmi-sound {
1890 compatible = "simple-audio-card";
1891 simple-audio-card,format = "i2s";
1892 simple-audio-card,mclk-fs = <256>;
1893 simple-audio-card,name = "hdmi-sound";
1896 simple-audio-card,cpu {
1897 sound-dai = <&i2s2>;
1899 simple-audio-card,codec {
1900 sound-dai = <&hdmi>;
1905 compatible = "rockchip,rk3399-dw-hdmi";
1913 clock-names = "iahb", "isfr", "cec", "grf", "ref";
1914 power-domains = <&power RK3399_PD_HDCP>;
1915 reg-io-width = <4>;
1917 #sound-dai-cells = <0>;
1922 #address-cells = <1>;
1923 #size-cells = <0>;
1927 remote-endpoint = <&vopb_out_hdmi>;
1931 remote-endpoint = <&vopl_out_hdmi>;
1938 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1943 clock-names = "ref", "pclk", "phy_cfg", "grf";
1944 power-domains = <&power RK3399_PD_VIO>;
1946 reset-names = "apb";
1948 #address-cells = <1>;
1949 #size-cells = <0>;
1953 #address-cells = <1>;
1954 #size-cells = <0>;
1958 #address-cells = <1>;
1959 #size-cells = <0>;
1963 remote-endpoint = <&vopb_out_mipi>;
1967 remote-endpoint = <&vopl_out_mipi>;
1974 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1979 clock-names = "ref", "pclk", "phy_cfg", "grf";
1980 power-domains = <&power RK3399_PD_VIO>;
1982 reset-names = "apb";
1984 #address-cells = <1>;
1985 #size-cells = <0>;
1986 #phy-cells = <0>;
1990 #address-cells = <1>;
1991 #size-cells = <0>;
1995 #address-cells = <1>;
1996 #size-cells = <0>;
2000 remote-endpoint = <&vopb_out_mipi1>;
2005 remote-endpoint = <&vopl_out_mipi1>;
2012 compatible = "rockchip,rk3399-edp";
2016 clock-names = "dp", "pclk", "grf";
2017 pinctrl-names = "default";
2018 pinctrl-0 = <&edp_hpd>;
2019 power-domains = <&power RK3399_PD_EDP>;
2021 reset-names = "dp";
2026 #address-cells = <1>;
2027 #size-cells = <0>;
2030 #address-cells = <1>;
2031 #size-cells = <0>;
2035 remote-endpoint = <&vopb_out_edp>;
2040 remote-endpoint = <&vopl_out_edp>;
2047 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2052 interrupt-names = "job", "mmu", "gpu";
2054 #cooling-cells = <2>;
2055 power-domains = <&power RK3399_PD_GPU>;
2060 compatible = "rockchip,rk3399-pinctrl";
2063 #address-cells = <2>;
2064 #size-cells = <2>;
2068 compatible = "rockchip,gpio-bank";
2073 gpio-controller;
2074 #gpio-cells = <0x2>;
2076 interrupt-controller;
2077 #interrupt-cells = <0x2>;
2081 compatible = "rockchip,gpio-bank";
2086 gpio-controller;
2087 #gpio-cells = <0x2>;
2089 interrupt-controller;
2090 #interrupt-cells = <0x2>;
2094 compatible = "rockchip,gpio-bank";
2099 gpio-controller;
2100 #gpio-cells = <0x2>;
2102 interrupt-controller;
2103 #interrupt-cells = <0x2>;
2107 compatible = "rockchip,gpio-bank";
2112 gpio-controller;
2113 #gpio-cells = <0x2>;
2115 interrupt-controller;
2116 #interrupt-cells = <0x2>;
2120 compatible = "rockchip,gpio-bank";
2125 gpio-controller;
2126 #gpio-cells = <0x2>;
2128 interrupt-controller;
2129 #interrupt-cells = <0x2>;
2132 pcfg_pull_up: pcfg-pull-up {
2133 bias-pull-up;
2136 pcfg_pull_down: pcfg-pull-down {
2137 bias-pull-down;
2140 pcfg_pull_none: pcfg-pull-none {
2141 bias-disable;
2144 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2145 bias-disable;
2146 drive-strength = <12>;
2149 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2150 bias-disable;
2151 drive-strength = <13>;
2154 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2155 bias-disable;
2156 drive-strength = <18>;
2159 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2160 bias-disable;
2161 drive-strength = <20>;
2164 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2165 bias-pull-up;
2166 drive-strength = <2>;
2169 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2170 bias-pull-up;
2171 drive-strength = <8>;
2174 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2175 bias-pull-up;
2176 drive-strength = <18>;
2179 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2180 bias-pull-up;
2181 drive-strength = <20>;
2184 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2185 bias-pull-down;
2186 drive-strength = <4>;
2189 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2190 bias-pull-down;
2191 drive-strength = <8>;
2194 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2195 bias-pull-down;
2196 drive-strength = <12>;
2199 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2200 bias-pull-down;
2201 drive-strength = <18>;
2204 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2205 bias-pull-down;
2206 drive-strength = <20>;
2209 pcfg_output_high: pcfg-output-high {
2210 output-high;
2213 pcfg_output_low: pcfg-output-low {
2214 output-low;
2217 pcfg_input_enable: pcfg-input-enable {
2218 input-enable;
2221 pcfg_input_pull_up: pcfg-input-pull-up {
2222 input-enable;
2223 bias-pull-up;
2224 drive-strength = <2>;
2227 pcfg_input_pull_down: pcfg-input-pull-down {
2228 input-enable;
2229 bias-pull-down;
2230 drive-strength = <2>;
2234 clk_32k: clk-32k {
2240 cif_clkin: cif-clkin {
2245 cif_clkouta: cif-clkouta {
2252 edp_hpd: edp-hpd {
2259 rgmii_pins: rgmii-pins {
2293 rmii_pins: rmii-pins {
2319 i2c0_xfer: i2c0-xfer {
2327 i2c1_xfer: i2c1-xfer {
2335 i2c2_xfer: i2c2-xfer {
2343 i2c3_xfer: i2c3-xfer {
2351 i2c4_xfer: i2c4-xfer {
2359 i2c5_xfer: i2c5-xfer {
2367 i2c6_xfer: i2c6-xfer {
2375 i2c7_xfer: i2c7-xfer {
2383 i2c8_xfer: i2c8-xfer {
2391 i2s0_2ch_bus: i2s0-2ch-bus {
2401 i2s0_8ch_bus: i2s0-8ch-bus {
2414 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
2429 i2s1_2ch_bus: i2s1-2ch-bus {
2438 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
2449 sdio0_bus1: sdio0-bus1 {
2454 sdio0_bus4: sdio0-bus4 {
2462 sdio0_cmd: sdio0-cmd {
2467 sdio0_clk: sdio0-clk {
2472 sdio0_cd: sdio0-cd {
2477 sdio0_pwr: sdio0-pwr {
2482 sdio0_bkpwr: sdio0-bkpwr {
2487 sdio0_wp: sdio0-wp {
2492 sdio0_int: sdio0-int {
2499 sdmmc_bus1: sdmmc-bus1 {
2504 sdmmc_bus4: sdmmc-bus4 {
2512 sdmmc_clk: sdmmc-clk {
2517 sdmmc_cmd: sdmmc-cmd {
2522 sdmmc_cd: sdmmc-cd {
2527 sdmmc_wp: sdmmc-wp {
2534 ap_pwroff: ap-pwroff {
2538 ddrio_pwroff: ddrio-pwroff {
2544 spdif_bus: spdif-bus {
2549 spdif_bus_1: spdif-bus-1 {
2556 spi0_clk: spi0-clk {
2560 spi0_cs0: spi0-cs0 {
2564 spi0_cs1: spi0-cs1 {
2568 spi0_tx: spi0-tx {
2572 spi0_rx: spi0-rx {
2579 spi1_clk: spi1-clk {
2583 spi1_cs0: spi1-cs0 {
2587 spi1_rx: spi1-rx {
2591 spi1_tx: spi1-tx {
2598 spi2_clk: spi2-clk {
2602 spi2_cs0: spi2-cs0 {
2606 spi2_rx: spi2-rx {
2610 spi2_tx: spi2-tx {
2617 spi3_clk: spi3-clk {
2621 spi3_cs0: spi3-cs0 {
2625 spi3_rx: spi3-rx {
2629 spi3_tx: spi3-tx {
2636 spi4_clk: spi4-clk {
2640 spi4_cs0: spi4-cs0 {
2644 spi4_rx: spi4-rx {
2648 spi4_tx: spi4-tx {
2655 spi5_clk: spi5-clk {
2659 spi5_cs0: spi5-cs0 {
2663 spi5_rx: spi5-rx {
2667 spi5_tx: spi5-tx {
2674 test_clkout0: test-clkout0 {
2679 test_clkout1: test-clkout1 {
2684 test_clkout2: test-clkout2 {
2691 otp_pin: otp-pin {
2695 otp_out: otp-out {
2701 uart0_xfer: uart0-xfer {
2707 uart0_cts: uart0-cts {
2712 uart0_rts: uart0-rts {
2719 uart1_xfer: uart1-xfer {
2727 uart2a_xfer: uart2a-xfer {
2735 uart2b_xfer: uart2b-xfer {
2743 uart2c_xfer: uart2c-xfer {
2751 uart3_xfer: uart3-xfer {
2757 uart3_cts: uart3-cts {
2762 uart3_rts: uart3-rts {
2769 uart4_xfer: uart4-xfer {
2777 uarthdcp_xfer: uarthdcp-xfer {
2785 pwm0_pin: pwm0-pin {
2790 pwm0_pin_pull_down: pwm0-pin-pull-down {
2795 vop0_pwm_pin: vop0-pwm-pin {
2800 vop1_pwm_pin: vop1-pwm-pin {
2807 pwm1_pin: pwm1-pin {
2812 pwm1_pin_pull_down: pwm1-pin-pull-down {
2819 pwm2_pin: pwm2-pin {
2824 pwm2_pin_pull_down: pwm2-pin-pull-down {
2831 pwm3a_pin: pwm3a-pin {
2838 pwm3b_pin: pwm3b-pin {
2845 hdmi_i2c_xfer: hdmi-i2c-xfer {
2851 hdmi_cec: hdmi-cec {
2858 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2863 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {