Lines Matching full:cru
6 #include <dt-bindings/clock/rk3368-cru.h>
183 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
184 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188 resets = <&cru SRST_MMC0>;
197 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
198 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202 resets = <&cru SRST_SDIO0>;
211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
212 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216 resets = <&cru SRST_EMMC>;
226 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
228 resets = <&cru SRST_SARADC>;
236 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
249 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
262 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
279 clocks = <&cru PCLK_I2C2>;
292 clocks = <&cru PCLK_I2C3>;
305 clocks = <&cru PCLK_I2C4>;
318 clocks = <&cru PCLK_I2C5>;
328 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
340 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
352 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
364 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
380 clocks = <&cru ACLK_DMAC_PERI>;
465 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
467 resets = <&cru SRST_TSADC>;
484 clocks = <&cru SCLK_MAC>,
485 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
486 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
487 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
499 clocks = <&cru HCLK_HOST0>;
508 clocks = <&cru HCLK_OTG0>;
525 clocks = <&cru ACLK_DMAC_BUS>;
532 clocks = <&cru PCLK_I2C0>;
549 clocks = <&cru PCLK_I2C1>;
561 clocks = <&cru PCLK_PWM1>;
571 clocks = <&cru PCLK_PWM1>;
579 clocks = <&cru PCLK_PWM1>;
589 clocks = <&cru PCLK_PWM1>;
596 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
613 clocks = <&cru PCLK_MAILBOX>;
654 clocks = <&cru ACLK_IEP>,
655 <&cru ACLK_ISP>,
656 <&cru ACLK_VIP>,
657 <&cru ACLK_RGA>,
658 <&cru ACLK_VOP>,
659 <&cru ACLK_VOP_IEP>,
660 <&cru DCLK_VOP>,
661 <&cru HCLK_IEP>,
662 <&cru HCLK_ISP>,
663 <&cru HCLK_RGA>,
664 <&cru HCLK_VIP>,
665 <&cru HCLK_VOP>,
666 <&cru HCLK_VIO_HDCPMMU>,
667 <&cru PCLK_EDP_CTRL>,
668 <&cru PCLK_HDMI_CTRL>,
669 <&cru PCLK_HDCP>,
670 <&cru PCLK_ISP>,
671 <&cru PCLK_VIP>,
672 <&cru PCLK_DPHYRX>,
673 <&cru PCLK_DPHYTX0>,
674 <&cru PCLK_MIPI_CSI>,
675 <&cru PCLK_MIPI_DSI0>,
676 <&cru SCLK_VOP0_PWM>,
677 <&cru SCLK_EDP_24M>,
678 <&cru SCLK_EDP>,
679 <&cru SCLK_HDCP>,
680 <&cru SCLK_ISP>,
681 <&cru SCLK_RGA>,
682 <&cru SCLK_HDMI_CEC>,
683 <&cru SCLK_HDMI_HDCP>;
703 clocks = <&cru ACLK_VIDEO>,
704 <&cru HCLK_VIDEO>,
705 <&cru SCLK_HEVC_CABAC>,
706 <&cru SCLK_HEVC_CORE>;
719 clocks = <&cru ACLK_GPU_CFG>,
720 <&cru ACLK_GPU_MEM>,
721 <&cru SCLK_GPU_CORE>;
747 cru: clock-controller@ff760000 { label
748 compatible = "rockchip,rk3368-cru";
770 clocks = <&cru PCLK_WDT>;
779 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
787 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
801 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
812 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
824 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
836 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
848 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
860 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
871 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
947 clocks = <&cru PCLK_EFUSE256>;
983 clocks = <&cru PCLK_GPIO0>;
996 clocks = <&cru PCLK_GPIO1>;
1009 clocks = <&cru PCLK_GPIO2>;
1022 clocks = <&cru PCLK_GPIO3>;