Lines Matching +full:pcfg +full:-
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
35 #address-cells = <2>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a53";
43 #cooling-cells = <2>;
44 cpu-idle-states = <&CPU_SLEEP>;
45 dynamic-power-coefficient = <120>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 operating-points-v2 = <&cpu0_opp_table>;
53 compatible = "arm,cortex-a53";
56 #cooling-cells = <2>;
57 cpu-idle-states = <&CPU_SLEEP>;
58 dynamic-power-coefficient = <120>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu0_opp_table>;
66 compatible = "arm,cortex-a53";
69 #cooling-cells = <2>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 dynamic-power-coefficient = <120>;
72 enable-method = "psci";
73 next-level-cache = <&l2>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a53";
82 #cooling-cells = <2>;
83 cpu-idle-states = <&CPU_SLEEP>;
84 dynamic-power-coefficient = <120>;
85 enable-method = "psci";
86 next-level-cache = <&l2>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
103 l2: l2-cache0 {
108 cpu0_opp_table: opp-table-0 {
109 compatible = "operating-points-v2";
110 opp-shared;
112 opp-408000000 {
113 opp-hz = /bits/ 64 <408000000>;
114 opp-microvolt = <950000>;
115 clock-latency-ns = <40000>;
116 opp-suspend;
118 opp-600000000 {
119 opp-hz = /bits/ 64 <600000000>;
120 opp-microvolt = <950000>;
121 clock-latency-ns = <40000>;
123 opp-816000000 {
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1000000>;
126 clock-latency-ns = <40000>;
128 opp-1008000000 {
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1100000>;
131 clock-latency-ns = <40000>;
133 opp-1200000000 {
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1225000>;
136 clock-latency-ns = <40000>;
138 opp-1296000000 {
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1300000>;
141 clock-latency-ns = <40000>;
145 analog_sound: analog-sound {
146 compatible = "simple-audio-card";
147 simple-audio-card,format = "i2s";
148 simple-audio-card,mclk-fs = <256>;
149 simple-audio-card,name = "Analog";
152 simple-audio-card,cpu {
153 sound-dai = <&i2s1>;
156 simple-audio-card,codec {
157 sound-dai = <&codec>;
161 arm-pmu {
162 compatible = "arm,cortex-a53-pmu";
167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
170 display_subsystem: display-subsystem {
171 compatible = "rockchip,display-subsystem";
175 hdmi_sound: hdmi-sound {
176 compatible = "simple-audio-card";
177 simple-audio-card,format = "i2s";
178 simple-audio-card,mclk-fs = <128>;
179 simple-audio-card,name = "HDMI";
182 simple-audio-card,cpu {
183 sound-dai = <&i2s0>;
186 simple-audio-card,codec {
187 sound-dai = <&hdmi>;
192 compatible = "arm,psci-1.0", "arm,psci-0.2";
197 compatible = "arm,armv8-timer";
205 compatible = "fixed-clock";
206 #clock-cells = <0>;
207 clock-frequency = <24000000>;
208 clock-output-names = "xin24m";
212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
216 clock-names = "i2s_clk", "i2s_hclk";
218 dma-names = "tx", "rx";
219 #sound-dai-cells = <0>;
224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
228 clock-names = "i2s_clk", "i2s_hclk";
230 dma-names = "tx", "rx";
231 #sound-dai-cells = <0>;
236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
240 clock-names = "i2s_clk", "i2s_hclk";
242 dma-names = "tx", "rx";
243 #sound-dai-cells = <0>;
248 compatible = "rockchip,rk3328-spdif";
252 clock-names = "mclk", "hclk";
254 dma-names = "tx";
255 pinctrl-names = "default";
256 pinctrl-0 = <&spdifm2_tx>;
257 #sound-dai-cells = <0>;
265 clock-names = "pdm_clk", "pdm_hclk";
267 dma-names = "rx";
268 pinctrl-names = "default", "sleep";
269 pinctrl-0 = <&pdmm0_clk
274 pinctrl-1 = <&pdmm0_clk_sleep
283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
286 io_domains: io-domains {
287 compatible = "rockchip,rk3328-io-voltage-domain";
292 compatible = "rockchip,rk3328-grf-gpio";
293 gpio-controller;
294 #gpio-cells = <2>;
297 power: power-controller {
298 compatible = "rockchip,rk3328-power-controller";
299 #power-domain-cells = <1>;
300 #address-cells = <1>;
301 #size-cells = <0>;
303 power-domain@RK3328_PD_HEVC {
305 #power-domain-cells = <0>;
307 power-domain@RK3328_PD_VIDEO {
313 #power-domain-cells = <0>;
315 power-domain@RK3328_PD_VPU {
318 #power-domain-cells = <0>;
322 reboot-mode {
323 compatible = "syscon-reboot-mode";
325 mode-normal = <BOOT_NORMAL>;
326 mode-recovery = <BOOT_RECOVERY>;
327 mode-bootloader = <BOOT_FASTBOOT>;
328 mode-loader = <BOOT_BL_DOWNLOAD>;
333 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
337 clock-names = "baudclk", "apb_pclk";
339 dma-names = "tx", "rx";
340 pinctrl-names = "default";
341 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
342 reg-io-width = <4>;
343 reg-shift = <2>;
348 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
352 clock-names = "baudclk", "apb_pclk";
354 dma-names = "tx", "rx";
355 pinctrl-names = "default";
356 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
357 reg-io-width = <4>;
358 reg-shift = <2>;
363 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
367 clock-names = "baudclk", "apb_pclk";
369 dma-names = "tx", "rx";
370 pinctrl-names = "default";
371 pinctrl-0 = <&uart2m1_xfer>;
372 reg-io-width = <4>;
373 reg-shift = <2>;
378 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
381 #address-cells = <1>;
382 #size-cells = <0>;
384 clock-names = "i2c", "pclk";
385 pinctrl-names = "default";
386 pinctrl-0 = <&i2c0_xfer>;
391 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
394 #address-cells = <1>;
395 #size-cells = <0>;
397 clock-names = "i2c", "pclk";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c1_xfer>;
404 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
407 #address-cells = <1>;
408 #size-cells = <0>;
410 clock-names = "i2c", "pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c2_xfer>;
417 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
420 #address-cells = <1>;
421 #size-cells = <0>;
423 clock-names = "i2c", "pclk";
424 pinctrl-names = "default";
425 pinctrl-0 = <&i2c3_xfer>;
430 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
433 #address-cells = <1>;
434 #size-cells = <0>;
436 clock-names = "spiclk", "apb_pclk";
438 dma-names = "tx", "rx";
439 pinctrl-names = "default";
440 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
445 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
452 compatible = "rockchip,rk3328-pwm";
455 clock-names = "pwm", "pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&pwm0_pin>;
458 #pwm-cells = <3>;
463 compatible = "rockchip,rk3328-pwm";
466 clock-names = "pwm", "pclk";
467 pinctrl-names = "default";
468 pinctrl-0 = <&pwm1_pin>;
469 #pwm-cells = <3>;
474 compatible = "rockchip,rk3328-pwm";
477 clock-names = "pwm", "pclk";
478 pinctrl-names = "default";
479 pinctrl-0 = <&pwm2_pin>;
480 #pwm-cells = <3>;
485 compatible = "rockchip,rk3328-pwm";
489 clock-names = "pwm", "pclk";
490 pinctrl-names = "default";
491 pinctrl-0 = <&pwmir_pin>;
492 #pwm-cells = <3>;
496 dmac: dma-controller@ff1f0000 {
501 arm,pl330-periph-burst;
503 clock-names = "apb_pclk";
504 #dma-cells = <1>;
507 thermal-zones {
508 soc_thermal: soc-thermal {
509 polling-delay-passive = <20>;
510 polling-delay = <1000>;
511 sustainable-power = <1000>;
513 thermal-sensors = <&tsadc 0>;
516 threshold: trip-point0 {
521 target: trip-point1 {
526 soc_crit: soc-crit {
533 cooling-maps {
536 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
548 compatible = "rockchip,rk3328-tsadc";
551 assigned-clocks = <&cru SCLK_TSADC>;
552 assigned-clock-rates = <50000>;
554 clock-names = "tsadc", "apb_pclk";
555 pinctrl-names = "init", "default", "sleep";
556 pinctrl-0 = <&otp_pin>;
557 pinctrl-1 = <&otp_out>;
558 pinctrl-2 = <&otp_pin>;
560 reset-names = "tsadc-apb";
562 rockchip,hw-tshut-temp = <100000>;
563 #thermal-sensor-cells = <1>;
568 compatible = "rockchip,rk3328-efuse";
570 #address-cells = <1>;
571 #size-cells = <1>;
573 clock-names = "pclk_efuse";
574 rockchip,efuse-size = <0x20>;
580 cpu_leakage: cpu-leakage@17 {
583 logic_leakage: logic-leakage@19 {
586 efuse_cpu_version: cpu-version@1a {
593 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
596 #io-channel-cells = <1>;
598 clock-names = "saradc", "apb_pclk";
600 reset-names = "saradc-apb";
605 compatible = "rockchip,rk3328-mali", "arm,mali-450";
614 interrupt-names = "gp",
622 clock-names = "bus", "core";
631 clock-names = "aclk", "iface";
632 #iommu-cells = <0>;
641 clock-names = "aclk", "iface";
642 #iommu-cells = <0>;
646 vpu: video-codec@ff350000 {
647 compatible = "rockchip,rk3328-vpu";
650 interrupt-names = "vdpu";
652 clock-names = "aclk", "hclk";
654 power-domains = <&power RK3328_PD_VPU>;
662 clock-names = "aclk", "iface";
663 #iommu-cells = <0>;
664 power-domains = <&power RK3328_PD_VPU>;
667 vdec: video-codec@ff360000 {
668 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
673 clock-names = "axi", "ahb", "cabac", "core";
674 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
676 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
678 power-domains = <&power RK3328_PD_VIDEO>;
686 clock-names = "aclk", "iface";
687 #iommu-cells = <0>;
688 power-domains = <&power RK3328_PD_VIDEO>;
692 compatible = "rockchip,rk3328-vop";
696 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
698 reset-names = "axi", "ahb", "dclk";
703 #address-cells = <1>;
704 #size-cells = <0>;
708 remote-endpoint = <&hdmi_in_vop>;
718 clock-names = "aclk", "iface";
719 #iommu-cells = <0>;
724 compatible = "rockchip,rk3328-dw-hdmi";
726 reg-io-width = <4>;
732 clock-names = "iahb",
736 phy-names = "hdmi";
737 pinctrl-names = "default";
738 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
740 #sound-dai-cells = <0>;
746 remote-endpoint = <&vop_out_hdmi>;
753 compatible = "rockchip,rk3328-codec";
756 clock-names = "pclk", "mclk";
758 #sound-dai-cells = <0>;
763 compatible = "rockchip,rk3328-hdmi-phy";
767 clock-names = "sysclk", "refoclk", "refpclk";
768 clock-output-names = "hdmi_phy";
769 #clock-cells = <0>;
770 nvmem-cells = <&efuse_cpu_version>;
771 nvmem-cell-names = "cpu-version";
772 #phy-cells = <0>;
776 cru: clock-controller@ff440000 {
777 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
780 #clock-cells = <1>;
781 #reset-cells = <1>;
782 assigned-clocks =
805 assigned-clock-parents =
809 assigned-clock-rates =
829 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
830 "simple-mfd";
832 #address-cells = <1>;
833 #size-cells = <1>;
836 compatible = "rockchip,rk3328-usb2phy";
839 clock-names = "phyclk";
840 clock-output-names = "usb480m_phy";
841 #clock-cells = <0>;
842 assigned-clocks = <&cru USB480M>;
843 assigned-clock-parents = <&u2phy>;
846 u2phy_otg: otg-port {
847 #phy-cells = <0>;
851 interrupt-names = "otg-bvalid", "otg-id",
856 u2phy_host: host-port {
857 #phy-cells = <0>;
859 interrupt-names = "linestate";
866 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
871 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
872 fifo-depth = <0x100>;
873 max-frequency = <150000000>;
878 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
883 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
884 fifo-depth = <0x100>;
885 max-frequency = <150000000>;
890 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
895 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
896 fifo-depth = <0x100>;
897 max-frequency = <150000000>;
902 compatible = "rockchip,rk3328-gmac";
905 interrupt-names = "macirq";
910 clock-names = "stmmaceth", "mac_clk_rx",
915 reset-names = "stmmaceth";
922 compatible = "rockchip,rk3328-gmac";
926 interrupt-names = "macirq";
931 clock-names = "stmmaceth", "mac_clk_rx",
936 reset-names = "stmmaceth";
937 phy-mode = "rmii";
938 phy-handle = <&phy>;
944 compatible = "snps,dwmac-mdio";
945 #address-cells = <1>;
946 #size-cells = <0>;
948 phy: ethernet-phy@0 {
949 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
953 pinctrl-names = "default";
954 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
955 phy-is-integrated;
961 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
966 clock-names = "otg";
968 g-np-tx-fifo-size = <16>;
969 g-rx-fifo-size = <280>;
970 g-tx-fifo-size = <256 128 128 64 32 16>;
972 phy-names = "usb2-phy";
977 compatible = "generic-ehci";
982 phy-names = "usb";
987 compatible = "generic-ohci";
992 phy-names = "usb";
997 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1002 clock-names = "ref_clk", "suspend_clk",
1006 snps,dis-del-phy-power-chg-quirk;
1008 snps,dis-tx-ipgap-linecheck-quirk;
1009 snps,dis-u2-freeclk-exists-quirk;
1015 gic: interrupt-controller@ff811000 {
1016 compatible = "arm,gic-400";
1017 #interrupt-cells = <3>;
1018 #address-cells = <0>;
1019 interrupt-controller;
1029 compatible = "rockchip,rk3328-pinctrl";
1031 #address-cells = <2>;
1032 #size-cells = <2>;
1036 compatible = "rockchip,gpio-bank";
1041 gpio-controller;
1042 #gpio-cells = <2>;
1044 interrupt-controller;
1045 #interrupt-cells = <2>;
1049 compatible = "rockchip,gpio-bank";
1054 gpio-controller;
1055 #gpio-cells = <2>;
1057 interrupt-controller;
1058 #interrupt-cells = <2>;
1062 compatible = "rockchip,gpio-bank";
1067 gpio-controller;
1068 #gpio-cells = <2>;
1070 interrupt-controller;
1071 #interrupt-cells = <2>;
1075 compatible = "rockchip,gpio-bank";
1080 gpio-controller;
1081 #gpio-cells = <2>;
1083 interrupt-controller;
1084 #interrupt-cells = <2>;
1087 pcfg_pull_up: pcfg-pull-up {
1088 bias-pull-up;
1091 pcfg_pull_down: pcfg-pull-down {
1092 bias-pull-down;
1095 pcfg_pull_none: pcfg-pull-none {
1096 bias-disable;
1099 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1100 bias-disable;
1101 drive-strength = <2>;
1104 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1105 bias-pull-up;
1106 drive-strength = <2>;
1109 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1110 bias-pull-up;
1111 drive-strength = <4>;
1114 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1115 bias-disable;
1116 drive-strength = <4>;
1119 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1120 bias-pull-down;
1121 drive-strength = <4>;
1124 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1125 bias-disable;
1126 drive-strength = <8>;
1129 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1130 bias-pull-up;
1131 drive-strength = <8>;
1134 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1135 bias-disable;
1136 drive-strength = <12>;
1139 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1140 bias-pull-up;
1141 drive-strength = <12>;
1144 pcfg_output_high: pcfg-output-high {
1145 output-high;
1148 pcfg_output_low: pcfg-output-low {
1149 output-low;
1152 pcfg_input_high: pcfg-input-high {
1153 bias-pull-up;
1154 input-enable;
1157 pcfg_input: pcfg-input {
1158 input-enable;
1162 i2c0_xfer: i2c0-xfer {
1169 i2c1_xfer: i2c1-xfer {
1176 i2c2_xfer: i2c2-xfer {
1183 i2c3_xfer: i2c3-xfer {
1187 i2c3_pins: i2c3-pins {
1195 hdmii2c_xfer: hdmii2c-xfer {
1201 pdm-0 {
1202 pdmm0_clk: pdmm0-clk {
1206 pdmm0_fsync: pdmm0-fsync {
1210 pdmm0_sdi0: pdmm0-sdi0 {
1214 pdmm0_sdi1: pdmm0-sdi1 {
1218 pdmm0_sdi2: pdmm0-sdi2 {
1222 pdmm0_sdi3: pdmm0-sdi3 {
1226 pdmm0_clk_sleep: pdmm0-clk-sleep {
1231 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1236 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1241 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1246 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1251 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1258 otp_pin: otp-pin {
1262 otp_out: otp-out {
1268 uart0_xfer: uart0-xfer {
1273 uart0_cts: uart0-cts {
1277 uart0_rts: uart0-rts {
1281 uart0_rts_pin: uart0-rts-pin {
1287 uart1_xfer: uart1-xfer {
1292 uart1_cts: uart1-cts {
1296 uart1_rts: uart1-rts {
1300 uart1_rts_pin: uart1-rts-pin {
1305 uart2-0 {
1306 uart2m0_xfer: uart2m0-xfer {
1312 uart2-1 {
1313 uart2m1_xfer: uart2m1-xfer {
1319 spi0-0 {
1320 spi0m0_clk: spi0m0-clk {
1324 spi0m0_cs0: spi0m0-cs0 {
1328 spi0m0_tx: spi0m0-tx {
1332 spi0m0_rx: spi0m0-rx {
1336 spi0m0_cs1: spi0m0-cs1 {
1341 spi0-1 {
1342 spi0m1_clk: spi0m1-clk {
1346 spi0m1_cs0: spi0m1-cs0 {
1350 spi0m1_tx: spi0m1-tx {
1354 spi0m1_rx: spi0m1-rx {
1358 spi0m1_cs1: spi0m1-cs1 {
1363 spi0-2 {
1364 spi0m2_clk: spi0m2-clk {
1368 spi0m2_cs0: spi0m2-cs0 {
1372 spi0m2_tx: spi0m2-tx {
1376 spi0m2_rx: spi0m2-rx {
1382 i2s1_mclk: i2s1-mclk {
1386 i2s1_sclk: i2s1-sclk {
1390 i2s1_lrckrx: i2s1-lrckrx {
1394 i2s1_lrcktx: i2s1-lrcktx {
1398 i2s1_sdi: i2s1-sdi {
1402 i2s1_sdo: i2s1-sdo {
1406 i2s1_sdio1: i2s1-sdio1 {
1410 i2s1_sdio2: i2s1-sdio2 {
1414 i2s1_sdio3: i2s1-sdio3 {
1418 i2s1_sleep: i2s1-sleep {
1432 i2s2-0 {
1433 i2s2m0_mclk: i2s2m0-mclk {
1437 i2s2m0_sclk: i2s2m0-sclk {
1441 i2s2m0_lrckrx: i2s2m0-lrckrx {
1445 i2s2m0_lrcktx: i2s2m0-lrcktx {
1449 i2s2m0_sdi: i2s2m0-sdi {
1453 i2s2m0_sdo: i2s2m0-sdo {
1457 i2s2m0_sleep: i2s2m0-sleep {
1468 i2s2-1 {
1469 i2s2m1_mclk: i2s2m1-mclk {
1473 i2s2m1_sclk: i2s2m1-sclk {
1477 i2s2m1_lrckrx: i2sm1-lrckrx {
1481 i2s2m1_lrcktx: i2s2m1-lrcktx {
1485 i2s2m1_sdi: i2s2m1-sdi {
1489 i2s2m1_sdo: i2s2m1-sdo {
1493 i2s2m1_sleep: i2s2m1-sleep {
1503 spdif-0 {
1504 spdifm0_tx: spdifm0-tx {
1509 spdif-1 {
1510 spdifm1_tx: spdifm1-tx {
1515 spdif-2 {
1516 spdifm2_tx: spdifm2-tx {
1521 sdmmc0-0 {
1522 sdmmc0m0_pwren: sdmmc0m0-pwren {
1526 sdmmc0m0_pin: sdmmc0m0-pin {
1531 sdmmc0-1 {
1532 sdmmc0m1_pwren: sdmmc0m1-pwren {
1536 sdmmc0m1_pin: sdmmc0m1-pin {
1542 sdmmc0_clk: sdmmc0-clk {
1546 sdmmc0_cmd: sdmmc0-cmd {
1550 sdmmc0_dectn: sdmmc0-dectn {
1554 sdmmc0_wrprt: sdmmc0-wrprt {
1558 sdmmc0_bus1: sdmmc0-bus1 {
1562 sdmmc0_bus4: sdmmc0-bus4 {
1569 sdmmc0_pins: sdmmc0-pins {
1583 sdmmc0ext_clk: sdmmc0ext-clk {
1587 sdmmc0ext_cmd: sdmmc0ext-cmd {
1591 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1595 sdmmc0ext_dectn: sdmmc0ext-dectn {
1599 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1603 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1611 sdmmc0ext_pins: sdmmc0ext-pins {
1625 sdmmc1_clk: sdmmc1-clk {
1629 sdmmc1_cmd: sdmmc1-cmd {
1633 sdmmc1_pwren: sdmmc1-pwren {
1637 sdmmc1_wrprt: sdmmc1-wrprt {
1641 sdmmc1_dectn: sdmmc1-dectn {
1645 sdmmc1_bus1: sdmmc1-bus1 {
1649 sdmmc1_bus4: sdmmc1-bus4 {
1656 sdmmc1_pins: sdmmc1-pins {
1671 emmc_clk: emmc-clk {
1675 emmc_cmd: emmc-cmd {
1679 emmc_pwren: emmc-pwren {
1683 emmc_rstnout: emmc-rstnout {
1687 emmc_bus1: emmc-bus1 {
1691 emmc_bus4: emmc-bus4 {
1699 emmc_bus8: emmc-bus8 {
1713 pwm0_pin: pwm0-pin {
1719 pwm1_pin: pwm1-pin {
1725 pwm2_pin: pwm2-pin {
1731 pwmir_pin: pwmir-pin {
1736 gmac-1 {
1737 rgmiim1_pins: rgmiim1-pins {
1786 rmiim1_pins: rmiim1-pins {
1825 fephyled_speed10: fephyled-speed10 {
1829 fephyled_duplex: fephyled-duplex {
1833 fephyled_rxm1: fephyled-rxm1 {
1837 fephyled_txm1: fephyled-txm1 {
1841 fephyled_linkm1: fephyled-linkm1 {
1847 tsadc_int: tsadc-int {
1850 tsadc_pin: tsadc-pin {
1856 hdmi_cec: hdmi-cec {
1860 hdmi_hpd: hdmi-hpd {
1865 cif-0 {
1866 dvp_d2d9_m0:dvp-d2d9-m0 {
1895 cif-1 {
1896 dvp_d2d9_m1:dvp-d2d9-m1 {