Lines Matching full:cru
6 #include <dt-bindings/clock/rk3328-cru.h>
42 clocks = <&cru ARMCLK>;
55 clocks = <&cru ARMCLK>;
68 clocks = <&cru ARMCLK>;
81 clocks = <&cru ARMCLK>;
215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
309 clocks = <&cru ACLK_RKVDEC>,
310 <&cru HCLK_RKVDEC>,
311 <&cru SCLK_VDEC_CABAC>,
312 <&cru SCLK_VDEC_CORE>;
317 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
336 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
351 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
366 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
383 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
396 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
409 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
422 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
435 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
448 clocks = <&cru PCLK_WDT>;
454 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
465 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
476 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
488 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
502 clocks = <&cru ACLK_DMAC>;
551 assigned-clocks = <&cru SCLK_TSADC>;
553 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
559 resets = <&cru SRST_TSADC>;
572 clocks = <&cru SCLK_EFUSE>;
597 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
599 resets = <&cru SRST_SARADC_P>;
621 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
623 resets = <&cru SRST_GPU_A>;
630 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
640 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
651 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
661 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
671 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
672 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
674 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
675 <&cru SCLK_VDEC_CORE>;
685 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
695 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
697 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
717 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
729 clocks = <&cru PCLK_HDMI>,
730 <&cru SCLK_HDMI_SFC>,
731 <&cru SCLK_RTC32K>;
755 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
766 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
776 cru: clock-controller@ff440000 { label
777 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
789 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
790 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
791 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
792 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
793 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
794 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
795 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
796 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
797 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
798 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
799 <&cru SCLK_WIFI>, <&cru ARMCLK>,
800 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
801 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
802 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
803 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
804 <&cru SCLK_RTC32K>;
806 <&cru HDMIPHY>, <&cru PLL_APLL>,
807 <&cru PLL_GPLL>, <&xin24m>,
842 assigned-clocks = <&cru USB480M>;
869 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
870 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
881 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
882 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
893 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
894 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
906 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
907 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
908 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
909 <&cru PCLK_MAC2IO>;
914 resets = <&cru SRST_GMAC2IO_A>;
927 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
928 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
929 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
930 <&cru SCLK_MAC2PHY_OUT>;
935 resets = <&cru SRST_GMAC2PHY_A>;
951 clocks = <&cru SCLK_MAC2PHY_OUT>;
952 resets = <&cru SRST_MACPHY>;
965 clocks = <&cru HCLK_OTG>;
980 clocks = <&cru HCLK_HOST0>, <&u2phy>;
990 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1000 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1001 <&cru ACLK_USB3OTG>;
1039 clocks = <&cru PCLK_GPIO0>;
1052 clocks = <&cru PCLK_GPIO1>;
1065 clocks = <&cru PCLK_GPIO2>;
1078 clocks = <&cru PCLK_GPIO3>;