Lines Matching +full:0 +full:xff300000
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0x0 0x0>;
54 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
96 arm,psci-suspend-param = <0x0010000>;
108 cpu0_opp_table: opp-table-0 {
206 #clock-cells = <0>;
213 reg = <0x0 0xff000000 0x0 0x1000>;
219 #sound-dai-cells = <0>;
225 reg = <0x0 0xff010000 0x0 0x1000>;
231 #sound-dai-cells = <0>;
237 reg = <0x0 0xff020000 0x0 0x1000>;
241 dmas = <&dmac 0>, <&dmac 1>;
243 #sound-dai-cells = <0>;
249 reg = <0x0 0xff030000 0x0 0x1000>;
256 pinctrl-0 = <&spdifm2_tx>;
257 #sound-dai-cells = <0>;
263 reg = <0x0 0xff040000 0x0 0x1000>;
269 pinctrl-0 = <&pdmm0_clk
284 reg = <0x0 0xff100000 0x0 0x1000>;
301 #size-cells = <0>;
305 #power-domain-cells = <0>;
313 #power-domain-cells = <0>;
318 #power-domain-cells = <0>;
324 offset = <0x5c8>;
334 reg = <0x0 0xff110000 0x0 0x100>;
341 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
349 reg = <0x0 0xff120000 0x0 0x100>;
356 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
364 reg = <0x0 0xff130000 0x0 0x100>;
371 pinctrl-0 = <&uart2m1_xfer>;
379 reg = <0x0 0xff150000 0x0 0x1000>;
382 #size-cells = <0>;
386 pinctrl-0 = <&i2c0_xfer>;
392 reg = <0x0 0xff160000 0x0 0x1000>;
395 #size-cells = <0>;
399 pinctrl-0 = <&i2c1_xfer>;
405 reg = <0x0 0xff170000 0x0 0x1000>;
408 #size-cells = <0>;
412 pinctrl-0 = <&i2c2_xfer>;
418 reg = <0x0 0xff180000 0x0 0x1000>;
421 #size-cells = <0>;
425 pinctrl-0 = <&i2c3_xfer>;
431 reg = <0x0 0xff190000 0x0 0x1000>;
434 #size-cells = <0>;
440 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
446 reg = <0x0 0xff1a0000 0x0 0x100>;
453 reg = <0x0 0xff1b0000 0x0 0x10>;
457 pinctrl-0 = <&pwm0_pin>;
464 reg = <0x0 0xff1b0010 0x0 0x10>;
468 pinctrl-0 = <&pwm1_pin>;
475 reg = <0x0 0xff1b0020 0x0 0x10>;
479 pinctrl-0 = <&pwm2_pin>;
486 reg = <0x0 0xff1b0030 0x0 0x10>;
491 pinctrl-0 = <&pwmir_pin>;
498 reg = <0x0 0xff1f0000 0x0 0x4000>;
499 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
513 thermal-sensors = <&tsadc 0>;
549 reg = <0x0 0xff250000 0x0 0x100>;
556 pinctrl-0 = <&otp_pin>;
569 reg = <0x0 0xff260000 0x0 0x50>;
574 rockchip,efuse-size = <0x20>;
578 reg = <0x07 0x10>;
581 reg = <0x17 0x1>;
584 reg = <0x19 0x1>;
587 reg = <0x1a 0x1>;
594 reg = <0x0 0xff280000 0x0 0x100>;
606 reg = <0x0 0xff300000 0x0 0x30000>;
628 reg = <0x0 0xff330200 0 0x100>;
632 #iommu-cells = <0>;
638 reg = <0x0 0xff340800 0x0 0x40>;
642 #iommu-cells = <0>;
648 reg = <0x0 0xff350000 0x0 0x800>;
659 reg = <0x0 0xff350800 0x0 0x40>;
663 #iommu-cells = <0>;
669 reg = <0x0 0xff360000 0x0 0x400>;
683 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
687 #iommu-cells = <0>;
693 reg = <0x0 0xff370000 0x0 0x3efc>;
704 #size-cells = <0>;
706 vop_out_hdmi: endpoint@0 {
707 reg = <0>;
715 reg = <0x0 0xff373f00 0x0 0x100>;
719 #iommu-cells = <0>;
725 reg = <0x0 0xff3c0000 0x0 0x20000>;
738 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
740 #sound-dai-cells = <0>;
754 reg = <0x0 0xff410000 0x0 0x1000>;
758 #sound-dai-cells = <0>;
764 reg = <0x0 0xff430000 0x0 0x10000>;
769 #clock-cells = <0>;
772 #phy-cells = <0>;
778 reg = <0x0 0xff440000 0x0 0x1000>;
810 <0>, <61440000>,
811 <0>, <24000000>,
831 reg = <0x0 0xff450000 0x0 0x10000>;
837 reg = <0x100 0x10>;
841 #clock-cells = <0>;
847 #phy-cells = <0>;
857 #phy-cells = <0>;
867 reg = <0x0 0xff500000 0x0 0x4000>;
872 fifo-depth = <0x100>;
879 reg = <0x0 0xff510000 0x0 0x4000>;
884 fifo-depth = <0x100>;
891 reg = <0x0 0xff520000 0x0 0x4000>;
896 fifo-depth = <0x100>;
903 reg = <0x0 0xff540000 0x0 0x10000>;
917 snps,txpbl = <0x4>;
923 reg = <0x0 0xff550000 0x0 0x10000>;
939 snps,txpbl = <0x4>;
946 #size-cells = <0>;
948 phy: ethernet-phy@0 {
950 reg = <0>;
954 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
963 reg = <0x0 0xff580000 0x0 0x40000>;
978 reg = <0x0 0xff5c0000 0x0 0x10000>;
988 reg = <0x0 0xff5d0000 0x0 0x10000>;
998 reg = <0x0 0xff600000 0x0 0x100000>;
1018 #address-cells = <0>;
1020 reg = <0x0 0xff811000 0 0x1000>,
1021 <0x0 0xff812000 0 0x2000>,
1022 <0x0 0xff814000 0 0x2000>,
1023 <0x0 0xff816000 0 0x2000>;
1037 reg = <0x0 0xff210000 0x0 0x100>;
1050 reg = <0x0 0xff220000 0x0 0x100>;
1063 reg = <0x0 0xff230000 0x0 0x100>;
1076 reg = <0x0 0xff240000 0x0 0x100>;
1184 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1185 <0 RK_PA6 2 &pcfg_pull_none>;
1189 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1190 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1196 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1197 <0 RK_PA6 1 &pcfg_pull_none>;
1201 pdm-0 {
1305 uart2-0 {
1319 spi0-0 {
1432 i2s2-0 {
1503 spdif-0 {
1505 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1517 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1521 sdmmc0-0 {
1533 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1537 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1688 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1693 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1701 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1771 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1773 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1775 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1777 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1779 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1781 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1783 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1810 <0 RK_PB3 1 &pcfg_pull_none>,
1812 <0 RK_PB4 1 &pcfg_pull_none>,
1814 <0 RK_PD0 1 &pcfg_pull_none>,
1816 <0 RK_PC3 1 &pcfg_pull_none>,
1818 <0 RK_PC0 1 &pcfg_pull_none>,
1820 <0 RK_PC1 1 &pcfg_pull_none>;
1826 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1830 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1857 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1861 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1865 cif-0 {