Lines Matching +full:pcfg +full:-
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
47 #cooling-cells = <2>;
48 dynamic-power-coefficient = <90>;
49 operating-points-v2 = <&cpu0_opp_table>;
50 cpu-idle-states = <&CPU_SLEEP>;
51 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP>;
61 next-level-cache = <&l2>;
66 compatible = "arm,cortex-a35";
68 enable-method = "psci";
69 operating-points-v2 = <&cpu0_opp_table>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 next-level-cache = <&l2>;
76 compatible = "arm,cortex-a35";
78 enable-method = "psci";
79 operating-points-v2 = <&cpu0_opp_table>;
80 cpu-idle-states = <&CPU_SLEEP>;
81 next-level-cache = <&l2>;
84 idle-states {
85 entry-method = "psci";
87 CPU_SLEEP: cpu-sleep {
88 compatible = "arm,idle-state";
89 local-timer-stop;
90 arm,psci-suspend-param = <0x0010000>;
91 entry-latency-us = <120>;
92 exit-latency-us = <250>;
93 min-residency-us = <900>;
97 l2: l2-cache {
102 cpu0_opp_table: opp-table-0 {
103 compatible = "operating-points-v2";
104 opp-shared;
106 opp-408000000 {
107 opp-hz = /bits/ 64 <408000000>;
108 opp-microvolt = <950000 950000 1340000>;
109 clock-latency-ns = <40000>;
110 opp-suspend;
112 opp-600000000 {
113 opp-hz = /bits/ 64 <600000000>;
114 opp-microvolt = <950000 950000 1340000>;
115 clock-latency-ns = <40000>;
117 opp-816000000 {
118 opp-hz = /bits/ 64 <816000000>;
119 opp-microvolt = <1025000 1025000 1340000>;
120 clock-latency-ns = <40000>;
122 opp-1008000000 {
123 opp-hz = /bits/ 64 <1008000000>;
124 opp-microvolt = <1125000 1125000 1340000>;
125 clock-latency-ns = <40000>;
129 arm-pmu {
130 compatible = "arm,cortex-a35-pmu";
135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
138 mac_clkin: external-mac-clock {
139 compatible = "fixed-clock";
140 clock-frequency = <50000000>;
141 clock-output-names = "mac_clkin";
142 #clock-cells = <0>;
146 compatible = "arm,psci-1.0";
151 compatible = "arm,armv8-timer";
159 compatible = "fixed-clock";
160 #clock-cells = <0>;
161 clock-frequency = <24000000>;
162 clock-output-names = "xin24m";
166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
169 reboot-mode {
170 compatible = "syscon-reboot-mode";
172 mode-bootloader = <BOOT_BL_DOWNLOAD>;
173 mode-loader = <BOOT_BL_DOWNLOAD>;
174 mode-normal = <BOOT_NORMAL>;
175 mode-recovery = <BOOT_RECOVERY>;
176 mode-fastboot = <BOOT_FASTBOOT>;
181 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
183 #address-cells = <1>;
184 #size-cells = <1>;
187 compatible = "rockchip,rk3308-usb2phy";
189 assigned-clocks = <&cru USB480M>;
190 assigned-clock-parents = <&u2phy>;
192 clock-names = "phyclk";
193 clock-output-names = "usb480m_phy";
194 #clock-cells = <0>;
197 u2phy_otg: otg-port {
201 interrupt-names = "otg-bvalid", "otg-id",
203 #phy-cells = <0>;
207 u2phy_host: host-port {
209 interrupt-names = "linestate";
210 #phy-cells = <0>;
217 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
219 #address-cells = <1>;
220 #size-cells = <1>;
224 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
226 #address-cells = <1>;
227 #size-cells = <1>;
231 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
234 clock-names = "i2c", "pclk";
236 pinctrl-names = "default";
237 pinctrl-0 = <&i2c0_xfer>;
238 #address-cells = <1>;
239 #size-cells = <0>;
244 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
247 clock-names = "i2c", "pclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&i2c1_xfer>;
251 #address-cells = <1>;
252 #size-cells = <0>;
257 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
260 clock-names = "i2c", "pclk";
262 pinctrl-names = "default";
263 pinctrl-0 = <&i2c2_xfer>;
264 #address-cells = <1>;
265 #size-cells = <0>;
270 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
273 clock-names = "i2c", "pclk";
275 pinctrl-names = "default";
276 pinctrl-0 = <&i2c3m0_xfer>;
277 #address-cells = <1>;
278 #size-cells = <0>;
283 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
291 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
295 clock-names = "baudclk", "apb_pclk";
296 reg-shift = <2>;
297 reg-io-width = <4>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
304 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
308 clock-names = "baudclk", "apb_pclk";
309 reg-shift = <2>;
310 reg-io-width = <4>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
317 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
321 clock-names = "baudclk", "apb_pclk";
322 reg-shift = <2>;
323 reg-io-width = <4>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart2m0_xfer>;
330 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
334 clock-names = "baudclk", "apb_pclk";
335 reg-shift = <2>;
336 reg-io-width = <4>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart3_xfer>;
343 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
347 clock-names = "baudclk", "apb_pclk";
348 reg-shift = <2>;
349 reg-io-width = <4>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
356 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
359 #address-cells = <1>;
360 #size-cells = <0>;
362 clock-names = "spiclk", "apb_pclk";
364 dma-names = "tx", "rx";
365 pinctrl-names = "default";
366 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
371 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
374 #address-cells = <1>;
375 #size-cells = <0>;
377 clock-names = "spiclk", "apb_pclk";
379 dma-names = "tx", "rx";
380 pinctrl-names = "default";
381 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
386 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
389 #address-cells = <1>;
390 #size-cells = <0>;
392 clock-names = "spiclk", "apb_pclk";
394 dma-names = "tx", "rx";
395 pinctrl-names = "default";
396 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
401 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
404 clock-names = "pwm", "pclk";
405 pinctrl-names = "default";
406 pinctrl-0 = <&pwm8_pin>;
407 #pwm-cells = <3>;
412 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
415 clock-names = "pwm", "pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&pwm9_pin>;
418 #pwm-cells = <3>;
423 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
426 clock-names = "pwm", "pclk";
427 pinctrl-names = "default";
428 pinctrl-0 = <&pwm10_pin>;
429 #pwm-cells = <3>;
434 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
437 clock-names = "pwm", "pclk";
438 pinctrl-names = "default";
439 pinctrl-0 = <&pwm11_pin>;
440 #pwm-cells = <3>;
445 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
448 clock-names = "pwm", "pclk";
449 pinctrl-names = "default";
450 pinctrl-0 = <&pwm4_pin>;
451 #pwm-cells = <3>;
456 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
459 clock-names = "pwm", "pclk";
460 pinctrl-names = "default";
461 pinctrl-0 = <&pwm5_pin>;
462 #pwm-cells = <3>;
467 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
470 clock-names = "pwm", "pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwm6_pin>;
473 #pwm-cells = <3>;
478 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
481 clock-names = "pwm", "pclk";
482 pinctrl-names = "default";
483 pinctrl-0 = <&pwm7_pin>;
484 #pwm-cells = <3>;
489 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
492 clock-names = "pwm", "pclk";
493 pinctrl-names = "default";
494 pinctrl-0 = <&pwm0_pin>;
495 #pwm-cells = <3>;
500 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
503 clock-names = "pwm", "pclk";
504 pinctrl-names = "default";
505 pinctrl-0 = <&pwm1_pin>;
506 #pwm-cells = <3>;
511 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
514 clock-names = "pwm", "pclk";
515 pinctrl-names = "default";
516 pinctrl-0 = <&pwm2_pin>;
517 #pwm-cells = <3>;
522 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
525 clock-names = "pwm", "pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&pwm3_pin>;
528 #pwm-cells = <3>;
533 compatible = "rockchip,rk3288-timer";
537 clock-names = "pclk", "timer";
541 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
545 clock-names = "saradc", "apb_pclk";
546 #io-channel-cells = <1>;
548 reset-names = "saradc-apb";
552 dmac0: dma-controller@ff2c0000 {
557 arm,pl330-periph-burst;
559 clock-names = "apb_pclk";
560 #dma-cells = <1>;
563 dmac1: dma-controller@ff2d0000 {
568 arm,pl330-periph-burst;
570 clock-names = "apb_pclk";
571 #dma-cells = <1>;
575 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
579 clock-names = "i2s_clk", "i2s_hclk";
581 dma-names = "tx", "rx";
583 reset-names = "reset-m", "reset-h";
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2s_2ch_0_sclk
593 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
597 clock-names = "i2s_clk", "i2s_hclk";
599 dma-names = "rx";
601 reset-names = "reset-m", "reset-h";
605 spdif_tx: spdif-tx@ff3a0000 {
606 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
610 clock-names = "mclk", "hclk";
612 dma-names = "tx";
613 pinctrl-names = "default";
614 pinctrl-0 = <&spdif_out>;
619 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
624 clock-names = "otg";
626 g-np-tx-fifo-size = <16>;
627 g-rx-fifo-size = <280>;
628 g-tx-fifo-size = <256 128 128 64 32 16>;
630 phy-names = "usb2-phy";
635 compatible = "generic-ehci";
640 phy-names = "usb";
645 compatible = "generic-ohci";
650 phy-names = "usb";
655 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
658 bus-width = <4>;
661 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
662 fifo-depth = <0x100>;
663 max-frequency = <150000000>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
670 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
673 bus-width = <8>;
676 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
677 fifo-depth = <0x100>;
678 max-frequency = <150000000>;
683 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
686 bus-width = <4>;
689 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
690 fifo-depth = <0x100>;
691 max-frequency = <150000000>;
692 pinctrl-names = "default";
693 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
697 nfc: nand-controller@ff4b0000 {
698 compatible = "rockchip,rk3308-nfc",
699 "rockchip,rv1108-nfc";
703 clock-names = "ahb", "nfc";
704 assigned-clocks = <&cru SCLK_NANDC>;
705 assigned-clock-rates = <150000000>;
706 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
708 pinctrl-names = "default";
713 compatible = "rockchip,rk3308-gmac";
716 interrupt-names = "macirq";
721 clock-names = "stmmaceth", "mac_clk_rx",
725 phy-mode = "rmii";
726 pinctrl-names = "default";
727 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
729 reset-names = "stmmaceth";
739 clock-names = "clk_sfc", "hclk_sfc";
740 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
741 pinctrl-names = "default";
745 cru: clock-controller@ff500000 {
746 compatible = "rockchip,rk3308-cru";
749 clock-names = "xin24m";
751 #clock-cells = <1>;
752 #reset-cells = <1>;
753 assigned-clocks = <&cru SCLK_RTC32K>;
754 assigned-clock-rates = <32768>;
757 gic: interrupt-controller@ff580000 {
758 compatible = "arm,gic-400";
764 #interrupt-cells = <3>;
765 interrupt-controller;
766 #address-cells = <0>;
770 compatible = "mmio-sram";
773 #address-cells = <1>;
774 #size-cells = <1>;
777 ddr-sram@0 {
782 vad_sram: vad-sram@8000 {
788 compatible = "rockchip,rk3308-pinctrl";
790 #address-cells = <2>;
791 #size-cells = <2>;
795 compatible = "rockchip,gpio-bank";
799 gpio-controller;
800 #gpio-cells = <2>;
801 interrupt-controller;
802 #interrupt-cells = <2>;
806 compatible = "rockchip,gpio-bank";
810 gpio-controller;
811 #gpio-cells = <2>;
812 interrupt-controller;
813 #interrupt-cells = <2>;
817 compatible = "rockchip,gpio-bank";
821 gpio-controller;
822 #gpio-cells = <2>;
823 interrupt-controller;
824 #interrupt-cells = <2>;
828 compatible = "rockchip,gpio-bank";
832 gpio-controller;
833 #gpio-cells = <2>;
834 interrupt-controller;
835 #interrupt-cells = <2>;
839 compatible = "rockchip,gpio-bank";
843 gpio-controller;
844 #gpio-cells = <2>;
845 interrupt-controller;
846 #interrupt-cells = <2>;
849 pcfg_pull_up: pcfg-pull-up {
850 bias-pull-up;
853 pcfg_pull_down: pcfg-pull-down {
854 bias-pull-down;
857 pcfg_pull_none: pcfg-pull-none {
858 bias-disable;
861 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
862 bias-disable;
863 drive-strength = <2>;
866 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
867 bias-pull-up;
868 drive-strength = <2>;
871 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
872 bias-pull-up;
873 drive-strength = <4>;
876 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
877 bias-disable;
878 drive-strength = <4>;
881 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
882 bias-pull-down;
883 drive-strength = <4>;
886 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
887 bias-disable;
888 drive-strength = <8>;
891 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
892 bias-pull-up;
893 drive-strength = <8>;
896 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
897 bias-disable;
898 drive-strength = <12>;
901 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
902 bias-pull-up;
903 drive-strength = <12>;
906 pcfg_pull_none_smt: pcfg-pull-none-smt {
907 bias-disable;
908 input-schmitt-enable;
911 pcfg_output_high: pcfg-output-high {
912 output-high;
915 pcfg_output_low: pcfg-output-low {
916 output-low;
919 pcfg_input_high: pcfg-input-high {
920 bias-pull-up;
921 input-enable;
924 pcfg_input: pcfg-input {
925 input-enable;
929 emmc_clk: emmc-clk {
934 emmc_cmd: emmc-cmd {
939 emmc_pwren: emmc-pwren {
944 emmc_rstn: emmc-rstn {
949 emmc_bus1: emmc-bus1 {
954 emmc_bus4: emmc-bus4 {
962 emmc_bus8: emmc-bus8 {
976 flash_csn0: flash-csn0 {
981 flash_rdy: flash-rdy {
986 flash_ale: flash-ale {
991 flash_cle: flash-cle {
996 flash_wrn: flash-wrn {
1001 flash_rdn: flash-rdn {
1006 flash_bus8: flash-bus8 {
1020 sfc_bus4: sfc-bus4 {
1028 sfc_bus2: sfc-bus2 {
1034 sfc_cs0: sfc-cs0 {
1039 sfc_clk: sfc-clk {
1046 rmii_pins: rmii-pins {
1068 mac_refclk_12ma: mac-refclk-12ma {
1073 mac_refclk: mac-refclk {
1079 gmac-m1 {
1080 rmiim1_pins: rmiim1-pins {
1102 macm1_refclk_12ma: macm1-refclk-12ma {
1107 macm1_refclk: macm1-refclk {
1114 i2c0_xfer: i2c0-xfer {
1122 i2c1_xfer: i2c1-xfer {
1130 i2c2_xfer: i2c2-xfer {
1137 i2c3-m0 {
1138 i2c3m0_xfer: i2c3m0-xfer {
1145 i2c3-m1 {
1146 i2c3m1_xfer: i2c3m1-xfer {
1153 i2c3-m2 {
1154 i2c3m2_xfer: i2c3m2-xfer {
1162 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1167 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1172 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1177 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1182 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1189 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1194 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1199 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1204 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1209 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1214 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1219 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1224 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1229 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1234 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1239 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1244 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1249 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1256 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1261 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1266 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1271 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1276 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1281 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1286 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1291 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1296 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1301 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1308 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1313 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1318 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1323 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1328 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1333 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1338 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1343 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1348 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1353 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1360 pdm_m0_clk: pdm-m0-clk {
1365 pdm_m0_sdi0: pdm-m0-sdi0 {
1370 pdm_m0_sdi1: pdm-m0-sdi1 {
1375 pdm_m0_sdi2: pdm-m0-sdi2 {
1380 pdm_m0_sdi3: pdm-m0-sdi3 {
1387 pdm_m1_clk: pdm-m1-clk {
1392 pdm_m1_sdi0: pdm-m1-sdi0 {
1397 pdm_m1_sdi1: pdm-m1-sdi1 {
1402 pdm_m1_sdi2: pdm-m1-sdi2 {
1407 pdm_m1_sdi3: pdm-m1-sdi3 {
1414 pdm_m2_clkm: pdm-m2-clkm {
1419 pdm_m2_clk: pdm-m2-clk {
1424 pdm_m2_sdi0: pdm-m2-sdi0 {
1429 pdm_m2_sdi1: pdm-m2-sdi1 {
1434 pdm_m2_sdi2: pdm-m2-sdi2 {
1439 pdm_m2_sdi3: pdm-m2-sdi3 {
1446 pwm0_pin: pwm0-pin {
1451 pwm0_pin_pull_down: pwm0-pin-pull-down {
1458 pwm1_pin: pwm1-pin {
1463 pwm1_pin_pull_down: pwm1-pin-pull-down {
1470 pwm2_pin: pwm2-pin {
1475 pwm2_pin_pull_down: pwm2-pin-pull-down {
1482 pwm3_pin: pwm3-pin {
1487 pwm3_pin_pull_down: pwm3-pin-pull-down {
1494 pwm4_pin: pwm4-pin {
1499 pwm4_pin_pull_down: pwm4-pin-pull-down {
1506 pwm5_pin: pwm5-pin {
1511 pwm5_pin_pull_down: pwm5-pin-pull-down {
1518 pwm6_pin: pwm6-pin {
1523 pwm6_pin_pull_down: pwm6-pin-pull-down {
1530 pwm7_pin: pwm7-pin {
1535 pwm7_pin_pull_down: pwm7-pin-pull-down {
1542 pwm8_pin: pwm8-pin {
1547 pwm8_pin_pull_down: pwm8-pin-pull-down {
1554 pwm9_pin: pwm9-pin {
1559 pwm9_pin_pull_down: pwm9-pin-pull-down {
1566 pwm10_pin: pwm10-pin {
1571 pwm10_pin_pull_down: pwm10-pin-pull-down {
1578 pwm11_pin: pwm11-pin {
1583 pwm11_pin_pull_down: pwm11-pin-pull-down {
1590 rtc_32k: rtc-32k {
1597 sdmmc_clk: sdmmc-clk {
1602 sdmmc_cmd: sdmmc-cmd {
1607 sdmmc_det: sdmmc-det {
1612 sdmmc_pwren: sdmmc-pwren {
1617 sdmmc_bus1: sdmmc-bus1 {
1622 sdmmc_bus4: sdmmc-bus4 {
1632 sdio_clk: sdio-clk {
1637 sdio_cmd: sdio-cmd {
1642 sdio_pwren: sdio-pwren {
1647 sdio_wrpt: sdio-wrpt {
1652 sdio_intn: sdio-intn {
1657 sdio_bus1: sdio-bus1 {
1662 sdio_bus4: sdio-bus4 {
1672 spdif_in: spdif-in {
1679 spdif_out: spdif-out {
1686 spi0_clk: spi0-clk {
1691 spi0_csn0: spi0-csn0 {
1696 spi0_miso: spi0-miso {
1701 spi0_mosi: spi0-mosi {
1708 spi1_clk: spi1-clk {
1713 spi1_csn0: spi1-csn0 {
1718 spi1_miso: spi1-miso {
1723 spi1_mosi: spi1-mosi {
1729 spi1-m1 {
1730 spi1m1_miso: spi1m1-miso {
1735 spi1m1_mosi: spi1m1-mosi {
1740 spi1m1_clk: spi1m1-clk {
1745 spi1m1_csn0: spi1m1-csn0 {
1752 spi2_clk: spi2-clk {
1757 spi2_csn0: spi2-csn0 {
1762 spi2_miso: spi2-miso {
1767 spi2_mosi: spi2-mosi {
1774 tsadc_otp_pin: tsadc-otp-pin {
1779 tsadc_otp_out: tsadc-otp-out {
1786 uart0_xfer: uart0-xfer {
1792 uart0_cts: uart0-cts {
1797 uart0_rts: uart0-rts {
1802 uart0_rts_pin: uart0-rts-pin {
1809 uart1_xfer: uart1-xfer {
1815 uart1_cts: uart1-cts {
1820 uart1_rts: uart1-rts {
1826 uart2-m0 {
1827 uart2m0_xfer: uart2m0-xfer {
1834 uart2-m1 {
1835 uart2m1_xfer: uart2m1-xfer {
1843 uart3_xfer: uart3-xfer {
1850 uart3-m1 {
1851 uart3m1_xfer: uart3m1-xfer {
1859 uart4_xfer: uart4-xfer {
1865 uart4_cts: uart4-cts {
1870 uart4_rts: uart4-rts {
1875 uart4_rts_pin: uart4-rts-pin {