Lines Matching full:cru
7 #include <dt-bindings/clock/rk3308-cru.h>
46 clocks = <&cru ARMCLK>;
189 assigned-clocks = <&cru USB480M>;
191 clocks = <&cru SCLK_USBPHY_REF>;
233 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
246 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
259 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
272 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
285 clocks = <&cru PCLK_WDT>;
294 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
307 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
320 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
333 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
346 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
361 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
376 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
391 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
403 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
414 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
425 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
436 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
447 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
458 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
469 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
480 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
491 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
502 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
513 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
524 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
536 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
544 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
547 resets = <&cru SRST_SARADC_P>;
558 clocks = <&cru ACLK_DMAC0>;
569 clocks = <&cru ACLK_DMAC1>;
578 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
582 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
596 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
600 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
609 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
623 clocks = <&cru HCLK_OTG>;
638 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
648 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
659 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
660 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
674 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
675 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
687 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
688 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
702 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
704 assigned-clocks = <&cru SCLK_NANDC>;
717 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
718 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
719 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
720 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
728 resets = <&cru SRST_MAC_A>;
738 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
745 cru: clock-controller@ff500000 { label
746 compatible = "rockchip,rk3308-cru";
753 assigned-clocks = <&cru SCLK_RTC32K>;
798 clocks = <&cru PCLK_GPIO0>;
809 clocks = <&cru PCLK_GPIO1>;
820 clocks = <&cru PCLK_GPIO2>;
831 clocks = <&cru PCLK_GPIO3>;
842 clocks = <&cru PCLK_GPIO4>;