Lines Matching +full:0 +full:xff4a0000
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
77 reg = <0x0 0x3>;
90 arm,psci-suspend-param = <0x0010000>;
102 cpu0_opp_table: opp-table-0 {
142 #clock-cells = <0>;
160 #clock-cells = <0>;
167 reg = <0x0 0xff000000 0x0 0x08000>;
171 offset = <0x500>;
182 reg = <0x0 0xff008000 0x0 0x4000>;
188 reg = <0x100 0x10>;
194 #clock-cells = <0>;
203 #phy-cells = <0>;
210 #phy-cells = <0>;
218 reg = <0x0 0xff00b000 0x0 0x1000>;
225 reg = <0x0 0xff00c000 0x0 0x1000>;
232 reg = <0x0 0xff040000 0x0 0x1000>;
237 pinctrl-0 = <&i2c0_xfer>;
239 #size-cells = <0>;
245 reg = <0x0 0xff050000 0x0 0x1000>;
250 pinctrl-0 = <&i2c1_xfer>;
252 #size-cells = <0>;
258 reg = <0x0 0xff060000 0x0 0x1000>;
263 pinctrl-0 = <&i2c2_xfer>;
265 #size-cells = <0>;
271 reg = <0x0 0xff070000 0x0 0x1000>;
276 pinctrl-0 = <&i2c3m0_xfer>;
278 #size-cells = <0>;
284 reg = <0x0 0xff080000 0x0 0x100>;
292 reg = <0x0 0xff0a0000 0x0 0x100>;
299 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
305 reg = <0x0 0xff0b0000 0x0 0x100>;
312 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
318 reg = <0x0 0xff0c0000 0x0 0x100>;
325 pinctrl-0 = <&uart2m0_xfer>;
331 reg = <0x0 0xff0d0000 0x0 0x100>;
338 pinctrl-0 = <&uart3_xfer>;
344 reg = <0x0 0xff0e0000 0x0 0x100>;
351 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
357 reg = <0x0 0xff120000 0x0 0x1000>;
360 #size-cells = <0>;
363 dmas = <&dmac0 0>, <&dmac0 1>;
366 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
372 reg = <0x0 0xff130000 0x0 0x1000>;
375 #size-cells = <0>;
381 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
387 reg = <0x0 0xff140000 0x0 0x1000>;
390 #size-cells = <0>;
396 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
402 reg = <0x0 0xff160000 0x0 0x10>;
406 pinctrl-0 = <&pwm8_pin>;
413 reg = <0x0 0xff160010 0x0 0x10>;
417 pinctrl-0 = <&pwm9_pin>;
424 reg = <0x0 0xff160020 0x0 0x10>;
428 pinctrl-0 = <&pwm10_pin>;
435 reg = <0x0 0xff160030 0x0 0x10>;
439 pinctrl-0 = <&pwm11_pin>;
446 reg = <0x0 0xff170000 0x0 0x10>;
450 pinctrl-0 = <&pwm4_pin>;
457 reg = <0x0 0xff170010 0x0 0x10>;
461 pinctrl-0 = <&pwm5_pin>;
468 reg = <0x0 0xff170020 0x0 0x10>;
472 pinctrl-0 = <&pwm6_pin>;
479 reg = <0x0 0xff170030 0x0 0x10>;
483 pinctrl-0 = <&pwm7_pin>;
490 reg = <0x0 0xff180000 0x0 0x10>;
494 pinctrl-0 = <&pwm0_pin>;
501 reg = <0x0 0xff180010 0x0 0x10>;
505 pinctrl-0 = <&pwm1_pin>;
512 reg = <0x0 0xff180020 0x0 0x10>;
516 pinctrl-0 = <&pwm2_pin>;
523 reg = <0x0 0xff180030 0x0 0x10>;
527 pinctrl-0 = <&pwm3_pin>;
534 reg = <0x0 0xff1a0000 0x0 0x20>;
542 reg = <0x0 0xff1e0000 0x0 0x100>;
554 reg = <0x0 0xff2c0000 0x0 0x4000>;
555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 reg = <0x0 0xff2d0000 0x0 0x4000>;
576 reg = <0x0 0xff350000 0x0 0x1000>;
585 pinctrl-0 = <&i2s_2ch_0_sclk
594 reg = <0x0 0xff360000 0x0 0x1000>;
607 reg = <0x0 0xff3a0000 0x0 0x1000>;
614 pinctrl-0 = <&spdif_out>;
621 reg = <0x0 0xff400000 0x0 0x40000>;
636 reg = <0x0 0xff440000 0x0 0x10000>;
646 reg = <0x0 0xff450000 0x0 0x10000>;
656 reg = <0x0 0xff480000 0x0 0x4000>;
662 fifo-depth = <0x100>;
665 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
671 reg = <0x0 0xff490000 0x0 0x4000>;
677 fifo-depth = <0x100>;
684 reg = <0x0 0xff4a0000 0x0 0x4000>;
690 fifo-depth = <0x100>;
693 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
700 reg = <0x0 0xff4b0000 0x0 0x4000>;
706 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
714 reg = <0x0 0xff4e0000 0x0 0x10000>;
727 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
736 reg = <0x0 0xff4c0000 0x0 0x4000>;
740 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
747 reg = <0x0 0xff500000 0x0 0x1000>;
759 reg = <0x0 0xff581000 0x0 0x1000>,
760 <0x0 0xff582000 0x0 0x2000>,
761 <0x0 0xff584000 0x0 0x2000>,
762 <0x0 0xff586000 0x0 0x2000>;
766 #address-cells = <0>;
771 reg = <0x0 0xfff80000 0x0 0x40000>;
772 ranges = <0 0x0 0xfff80000 0x40000>;
777 ddr-sram@0 {
778 reg = <0x0 0x8000>;
783 reg = <0x8000 0x38000>;
796 reg = <0x0 0xff220000 0x0 0x100>;
807 reg = <0x0 0xff230000 0x0 0x100>;
818 reg = <0x0 0xff240000 0x0 0x100>;
829 reg = <0x0 0xff250000 0x0 0x100>;
840 reg = <0x0 0xff260000 0x0 0x100>;
1124 <0 RK_PB3 1 &pcfg_pull_none_smt>,
1125 <0 RK_PB4 1 &pcfg_pull_none_smt>;
1140 <0 RK_PB7 2 &pcfg_pull_none_smt>,
1141 <0 RK_PC0 2 &pcfg_pull_none_smt>;
1162 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1167 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1172 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1177 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1182 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1189 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1194 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1199 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1204 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1209 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1214 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1219 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1224 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1229 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1234 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1239 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1244 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1249 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1448 <0 RK_PB5 1 &pcfg_pull_none>;
1453 <0 RK_PB5 1 &pcfg_pull_down>;
1460 <0 RK_PB6 1 &pcfg_pull_none>;
1465 <0 RK_PB6 1 &pcfg_pull_down>;
1472 <0 RK_PB7 1 &pcfg_pull_none>;
1477 <0 RK_PB7 1 &pcfg_pull_down>;
1484 <0 RK_PC0 1 &pcfg_pull_none>;
1489 <0 RK_PC0 1 &pcfg_pull_down>;
1496 <0 RK_PA1 2 &pcfg_pull_none>;
1501 <0 RK_PA1 2 &pcfg_pull_down>;
1508 <0 RK_PC1 2 &pcfg_pull_none>;
1513 <0 RK_PC1 2 &pcfg_pull_down>;
1520 <0 RK_PC2 2 &pcfg_pull_none>;
1525 <0 RK_PC2 2 &pcfg_pull_down>;
1592 <0 RK_PC3 1 &pcfg_pull_none>;
1609 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1644 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1649 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1654 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1674 <0 RK_PC2 1 &pcfg_pull_none>;
1681 <0 RK_PC1 1 &pcfg_pull_none>;
1776 <0 RK_PB2 0 &pcfg_pull_none>;
1781 <0 RK_PB2 1 &pcfg_pull_none>;
1804 <2 RK_PA3 0 &pcfg_pull_none>;
1853 <0 RK_PC2 3 &pcfg_pull_up>,
1854 <0 RK_PC1 3 &pcfg_pull_up>;
1877 <4 RK_PA7 0 &pcfg_pull_none>;