Lines Matching full:cru
6 #include <dt-bindings/clock/px30-cru.h>
47 clocks = <&cru ARMCLK>;
59 clocks = <&cru ARMCLK>;
71 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
249 clocks = <&cru HCLK_HOST>,
250 <&cru HCLK_OTG>,
251 <&cru SCLK_OTG_ADP>;
257 clocks = <&cru HCLK_SDMMC>,
258 <&cru SCLK_SDMMC>;
264 clocks = <&cru ACLK_GMAC>,
265 <&cru PCLK_GMAC>,
266 <&cru SCLK_MAC_REF>,
267 <&cru SCLK_GMAC_RX_TX>;
273 clocks = <&cru HCLK_NANDC>,
274 <&cru HCLK_EMMC>,
275 <&cru HCLK_SDIO>,
276 <&cru HCLK_SFC>,
277 <&cru SCLK_EMMC>,
278 <&cru SCLK_NANDC>,
279 <&cru SCLK_SDIO>,
280 <&cru SCLK_SFC>;
287 clocks = <&cru ACLK_VPU>,
288 <&cru HCLK_VPU>,
289 <&cru SCLK_CORE_VPU>;
295 clocks = <&cru ACLK_RGA>,
296 <&cru ACLK_VOPB>,
297 <&cru ACLK_VOPL>,
298 <&cru DCLK_VOPB>,
299 <&cru DCLK_VOPL>,
300 <&cru HCLK_RGA>,
301 <&cru HCLK_VOPB>,
302 <&cru HCLK_VOPL>,
303 <&cru PCLK_MIPI_DSI>,
304 <&cru SCLK_RGA_CORE>,
305 <&cru SCLK_VOPB_PWM>;
312 clocks = <&cru ACLK_CIF>,
313 <&cru ACLK_ISP>,
314 <&cru HCLK_CIF>,
315 <&cru HCLK_ISP>,
316 <&cru SCLK_ISP>;
324 clocks = <&cru SCLK_GPU>;
372 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
377 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
394 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
409 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
479 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
494 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
509 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
524 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
539 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
553 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
566 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
579 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
592 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
606 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
621 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
635 clocks = <&cru PCLK_WDT_NS>;
643 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
654 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
665 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
676 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
687 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
698 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
709 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
720 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
732 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
742 clocks = <&cru ACLK_DMAC>;
751 assigned-clocks = <&cru SCLK_TSADC>;
753 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
755 resets = <&cru SRST_TSADC>;
772 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
774 resets = <&cru SRST_SARADC_P>;
782 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
783 <&cru PCLK_OTP_PHY>;
785 resets = <&cru SRST_OTP_PHY>;
803 cru: clock-controller@ff2b0000 { label
804 compatible = "rockchip,px30-cru";
812 assigned-clocks = <&cru PLL_NPLL>,
813 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
814 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
815 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
853 assigned-clocks = <&cru USB480M>;
880 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
882 resets = <&cru SRST_MIPIDSIPHY_P>;
892 clocks = <&cru PCLK_MIPICSIPHY>;
896 resets = <&cru SRST_MIPICSIPHY_P>;
907 clocks = <&cru HCLK_OTG>;
923 clocks = <&cru HCLK_HOST>;
934 clocks = <&cru HCLK_HOST>;
946 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
947 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
948 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
949 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
959 resets = <&cru SRST_GMAC_A>;
968 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
969 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
984 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
985 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1000 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1001 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1016 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1028 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1030 assigned-clocks = <&cru SCLK_NANDC>;
1067 clocks = <&cru SCLK_GPU>;
1080 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1090 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1100 clocks = <&cru PCLK_MIPI_DSI>;
1105 resets = <&cru SRST_MIPIDSI_HOST_P>;
1138 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1139 <&cru HCLK_VOPB>;
1141 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1167 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1178 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1179 <&cru HCLK_VOPL>;
1181 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1207 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1221 clocks = <&cru SCLK_ISP>,
1222 <&cru ACLK_ISP>,
1223 <&cru HCLK_ISP>,
1224 <&cru PCLK_ISP>;
1248 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1379 clocks = <&cru PCLK_GPIO1>;
1391 clocks = <&cru PCLK_GPIO2>;
1403 clocks = <&cru PCLK_GPIO3>;