Lines Matching +full:0 +full:xff2f0000
40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
69 reg = <0x0 0x2>;
81 reg = <0x0 0x3>;
96 arm,psci-suspend-param = <0x0010000>;
105 arm,psci-suspend-param = <0x1010000>;
113 cpu0_opp_table: opp-table-0 {
164 #clock-cells = <0>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
231 #clock-cells = <0>;
238 reg = <0x0 0xff000000 0x0 0x1000>;
244 #size-cells = <0>;
253 #power-domain-cells = <0>;
260 #power-domain-cells = <0>;
269 #power-domain-cells = <0>;
283 #power-domain-cells = <0>;
291 #power-domain-cells = <0>;
308 #power-domain-cells = <0>;
320 #power-domain-cells = <0>;
326 #power-domain-cells = <0>;
333 reg = <0x0 0xff010000 0x0 0x1000>;
344 offset = <0x200>;
355 reg = <0x0 0xff030000 0x0 0x100>;
359 dmas = <&dmac 0>, <&dmac 1>;
364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
370 reg = <0x0 0xff060000 0x0 0x1000>;
380 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
386 #sound-dai-cells = <0>;
392 reg = <0x0 0xff070000 0x0 0x1000>;
399 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
401 #sound-dai-cells = <0>;
407 reg = <0x0 0xff080000 0x0 0x1000>;
414 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
416 #sound-dai-cells = <0>;
423 #address-cells = <0>;
425 reg = <0x0 0xff131000 0 0x1000>,
426 <0x0 0xff132000 0 0x2000>,
427 <0x0 0xff134000 0 0x2000>,
428 <0x0 0xff136000 0 0x2000>;
435 reg = <0x0 0xff140000 0x0 0x1000>;
454 #size-cells = <0>;
456 port@0 {
457 reg = <0>;
459 #size-cells = <0>;
461 lvds_vopb_in: endpoint@0 {
462 reg = <0>;
477 reg = <0x0 0xff158000 0x0 0x100>;
486 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
492 reg = <0x0 0xff160000 0x0 0x100>;
501 pinctrl-0 = <&uart2m0_xfer>;
507 reg = <0x0 0xff168000 0x0 0x100>;
516 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
522 reg = <0x0 0xff170000 0x0 0x100>;
531 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
537 reg = <0x0 0xff178000 0x0 0x100>;
546 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
552 reg = <0x0 0xff180000 0x0 0x1000>;
557 pinctrl-0 = <&i2c0_xfer>;
559 #size-cells = <0>;
565 reg = <0x0 0xff190000 0x0 0x1000>;
570 pinctrl-0 = <&i2c1_xfer>;
572 #size-cells = <0>;
578 reg = <0x0 0xff1a0000 0x0 0x1000>;
583 pinctrl-0 = <&i2c2_xfer>;
585 #size-cells = <0>;
591 reg = <0x0 0xff1b0000 0x0 0x1000>;
596 pinctrl-0 = <&i2c3_xfer>;
598 #size-cells = <0>;
604 reg = <0x0 0xff1d0000 0x0 0x1000>;
611 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
613 #size-cells = <0>;
619 reg = <0x0 0xff1d8000 0x0 0x1000>;
626 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
628 #size-cells = <0>;
634 reg = <0x0 0xff1e0000 0x0 0x100>;
642 reg = <0x0 0xff200000 0x0 0x10>;
646 pinctrl-0 = <&pwm0_pin>;
653 reg = <0x0 0xff200010 0x0 0x10>;
657 pinctrl-0 = <&pwm1_pin>;
664 reg = <0x0 0xff200020 0x0 0x10>;
668 pinctrl-0 = <&pwm2_pin>;
675 reg = <0x0 0xff200030 0x0 0x10>;
679 pinctrl-0 = <&pwm3_pin>;
686 reg = <0x0 0xff208000 0x0 0x10>;
690 pinctrl-0 = <&pwm4_pin>;
697 reg = <0x0 0xff208010 0x0 0x10>;
701 pinctrl-0 = <&pwm5_pin>;
708 reg = <0x0 0xff208020 0x0 0x10>;
712 pinctrl-0 = <&pwm6_pin>;
719 reg = <0x0 0xff208030 0x0 0x10>;
723 pinctrl-0 = <&pwm7_pin>;
730 reg = <0x0 0xff210000 0x0 0x1000>;
738 reg = <0x0 0xff240000 0x0 0x4000>;
749 reg = <0x0 0xff280000 0x0 0x100>;
760 pinctrl-0 = <&tsadc_otp_pin>;
769 reg = <0x0 0xff288000 0x0 0x100>;
781 reg = <0x0 0xff290000 0x0 0x4000>;
792 reg = <0x07 0x10>;
795 reg = <0x17 0x1>;
798 reg = <0x1e 0x1>;
805 reg = <0x0 0xff2b0000 0x0 0x1000>;
825 reg = <0x0 0xff2bc000 0x0 0x1000>;
843 reg = <0x0 0xff2c0000 0x0 0x10000>;
849 reg = <0x100 0x20>;
852 #clock-cells = <0>;
859 #phy-cells = <0>;
866 #phy-cells = <0>;
879 reg = <0x0 0xff2e0000 0x0 0x10000>;
884 #phy-cells = <0>;
891 reg = <0x0 0xff2f0000 0x0 0x4000>;
894 #phy-cells = <0>;
905 reg = <0x0 0xff300000 0x0 0x40000>;
921 reg = <0x0 0xff340000 0x0 0x10000>;
932 reg = <0x0 0xff350000 0x0 0x10000>;
943 reg = <0x0 0xff360000 0x0 0x10000>;
957 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
966 reg = <0x0 0xff370000 0x0 0x4000>;
972 fifo-depth = <0x100>;
975 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
982 reg = <0x0 0xff380000 0x0 0x4000>;
988 fifo-depth = <0x100>;
991 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
998 reg = <0x0 0xff390000 0x0 0x4000>;
1004 fifo-depth = <0x100>;
1007 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1014 reg = <0x0 0xff3a0000 0x0 0x4000>;
1018 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1026 reg = <0x0 0xff3b0000 0x0 0x4000>;
1033 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1062 reg = <0x0 0xff400000 0x0 0x4000>;
1076 reg = <0x0 0xff442000 0x0 0x800>;
1088 reg = <0x0 0xff442800 0x0 0x100>;
1092 #iommu-cells = <0>;
1098 reg = <0x0 0xff450000 0x0 0x10000>;
1109 #size-cells = <0>;
1114 #size-cells = <0>;
1116 port@0 {
1117 reg = <0>;
1119 #size-cells = <0>;
1121 dsi_in_vopb: endpoint@0 {
1122 reg = <0>;
1136 reg = <0x0 0xff460000 0x0 0xefc>;
1149 #size-cells = <0>;
1151 vopb_out_dsi: endpoint@0 {
1152 reg = <0>;
1165 reg = <0x0 0xff460f00 0x0 0x100>;
1170 #iommu-cells = <0>;
1176 reg = <0x0 0xff470000 0x0 0xefc>;
1189 #size-cells = <0>;
1191 vopl_out_dsi: endpoint@0 {
1192 reg = <0>;
1205 reg = <0x0 0xff470f00 0x0 0x100>;
1210 #iommu-cells = <0>;
1216 reg = <0x0 0xff4a0000 0x0 0x8000>;
1234 #size-cells = <0>;
1236 port@0 {
1237 reg = <0>;
1239 #size-cells = <0>;
1246 reg = <0x0 0xff4a8000 0x0 0x100>;
1252 #iommu-cells = <0>;
1257 reg = <0x0 0xff518000 0x0 0x20>;
1262 reg = <0x0 0xff520000 0x0 0x20>;
1267 reg = <0x0 0xff52c000 0x0 0x20>;
1272 reg = <0x0 0xff538000 0x0 0x20>;
1277 reg = <0x0 0xff538080 0x0 0x20>;
1282 reg = <0x0 0xff538100 0x0 0x20>;
1287 reg = <0x0 0xff538180 0x0 0x20>;
1292 reg = <0x0 0xff540000 0x0 0x20>;
1297 reg = <0x0 0xff540080 0x0 0x20>;
1302 reg = <0x0 0xff548000 0x0 0x20>;
1307 reg = <0x0 0xff548080 0x0 0x20>;
1312 reg = <0x0 0xff548100 0x0 0x20>;
1317 reg = <0x0 0xff548180 0x0 0x20>;
1322 reg = <0x0 0xff548200 0x0 0x20>;
1327 reg = <0x0 0xff550000 0x0 0x20>;
1332 reg = <0x0 0xff550080 0x0 0x20>;
1337 reg = <0x0 0xff550100 0x0 0x20>;
1342 reg = <0x0 0xff550180 0x0 0x20>;
1347 reg = <0x0 0xff558000 0x0 0x20>;
1352 reg = <0x0 0xff558080 0x0 0x20>;
1365 reg = <0x0 0xff040000 0x0 0x100>;
1377 reg = <0x0 0xff250000 0x0 0x100>;
1389 reg = <0x0 0xff260000 0x0 0x100>;
1401 reg = <0x0 0xff270000 0x0 0x100>;
1493 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1494 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1501 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1502 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1525 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1530 <0 RK_PA6 1 &pcfg_pull_none>;
1537 <0 RK_PB2 1 &pcfg_pull_up>,
1538 <0 RK_PB3 1 &pcfg_pull_up>;
1543 <0 RK_PB4 1 &pcfg_pull_none>;
1548 <0 RK_PB5 1 &pcfg_pull_none>;
1589 <0 RK_PC0 2 &pcfg_pull_up>,
1590 <0 RK_PC1 2 &pcfg_pull_up>;
1595 <0 RK_PC2 2 &pcfg_pull_none>;
1600 <0 RK_PC3 2 &pcfg_pull_none>;
1953 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
2256 <0 RK_PB7 1 &pcfg_pull_none>;
2263 <0 RK_PC0 1 &pcfg_pull_none>;
2277 <0 RK_PC1 1 &pcfg_pull_none>;