Lines Matching +full:0 +full:x2655

18 		#clock-cells = <0>;
20 		clock-frequency = <0>;
25 		#clock-cells = <0>;
27 		clock-frequency = <0>;
33 		#clock-cells = <0>;
34 		clock-frequency = <0>;
40 		#clock-cells = <0>;
42 		clock-frequency = <0>;
45 	cluster0_opp: opp-table-0 {
74 		#size-cells = <0>;
87 		cpu0: cpu@0 {
89 			reg = <0>;
100 			reg = <0x100>;
108 		L3_CA55: cache-controller-0 {
111 			cache-size = <0x40000>;
174 			reg = <0 0x10049c00 0 0x400>;
185 			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
188 			#sound-dai-cells = <0>;
195 			reg = <0 0x1004a000 0 0x400>;
206 			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
209 			#sound-dai-cells = <0>;
216 			reg = <0 0x1004a400 0 0x400>;
227 			dmas = <&dmac 0x265f>;
230 			#sound-dai-cells = <0>;
237 			reg = <0 0x1004a800 0 0x400>;
248 			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
251 			#sound-dai-cells = <0>;
257 			reg = <0 0x1004ac00 0 0x400>;
264 			dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
269 			#size-cells = <0>;
275 			reg = <0 0x1004b000 0 0x400>;
282 			dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
287 			#size-cells = <0>;
293 			reg = <0 0x1004b400 0 0x400>;
300 			dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
305 			#size-cells = <0>;
312 			reg = <0 0x1004b800 0 0x400>;
331 			reg = <0 0x1004bc00 0 0x400>;
350 			reg = <0 0x1004c000 0 0x400>;
369 			reg = <0 0x1004c400 0 0x400>;
388 			reg = <0 0x1004c800 0 0x400>;
406 			reg = <0 0x1004d000 0 0x400>;
421 			reg = <0 0x1004d400 0 0x400>;
436 			reg = <0 0x10050000 0 0x8000>;
470 			#size-cells = <0>;
472 			reg = <0 0x10058000 0 0x400>;
492 			#size-cells = <0>;
494 			reg = <0 0x10058400 0 0x400>;
514 			#size-cells = <0>;
516 			reg = <0 0x10058800 0 0x400>;
536 			#size-cells = <0>;
538 			reg = <0 0x10058c00 0 0x400>;
558 			reg = <0 0x10059000 0 0x400>;
570 			#size-cells = <0>;
572 			channel@0 {
573 				reg = <0>;
601 			reg = <0 0x10059400 0 0x400>;
611 			reg = <0 0x10060000 0 0x10000>,
612 			      <0 0x20000000 0 0x10000000>,
613 			      <0 0x10070000 0 0x10000>;
621 			#size-cells = <0>;
627 			reg = <0 0x11010000 0 0x10000>;
632 			#power-domain-cells = <0>;
637 			reg = <0 0x11020000 0 0x10000>;
650 			reg = <0 0x11030000 0 0x10000>;
657 			gpio-ranges = <&pinctrl 0 0 392>;
669 			#address-cells = <0>;
671 			reg = <0 0x110a0000 0 0x10000>;
672 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
723 			reg = <0 0x11820000 0 0x10000>,
724 			      <0 0x11830000 0 0x10000>;
759 			reg = <0x0 0x11840000 0x0 0x10000>;
780 			#address-cells = <0>;
782 			reg = <0x0 0x11900000 0 0x40000>,
783 			      <0x0 0x11940000 0 0x60000>;
790 			reg = <0x0 0x11c00000 0 0x10000>;
806 			reg = <0x0 0x11c10000 0 0x10000>;
822 			reg = <0 0x11c20000 0 0x10000>;
835 			#size-cells = <0>;
842 			reg = <0 0x11c30000 0 0x10000>;
855 			#size-cells = <0>;
862 			reg = <0 0x11c40000 0 0x10000>;
872 			reg = <0 0x11c50000 0 0x100>;
876 			resets = <&phyrst 0>,
886 			reg = <0 0x11c70000 0 0x100>;
900 			reg = <0 0x11c50100 0 0x100>;
904 			resets = <&phyrst 0>,
915 			reg = <0 0x11c70100 0 0x100>;
931 			reg = <0 0x11c50200 0 0x700>;
935 			resets = <&phyrst 0>;
944 			reg = <0 0x11c70200 0 0x700>;
957 			reg = <0 0x11c60000 0 0x10000>;
964 			resets = <&phyrst 0>,
976 			reg = <0 0x12800800 0 0x400>;
991 			reg = <0 0x12800C00 0 0x400>;
1006 			reg = <0 0x12800400 0 0x400>;
1021 			reg = <0x0 0x12801000 0x0 0x400>;
1032 			reg = <0x0 0x12801400 0x0 0x400>;
1043 			reg = <0x0 0x12801800 0x0 0x400>;
1056 			thermal-sensors = <&tsu 0>;
1062 					cooling-device = <&cpu0 0 2>;