Lines Matching full:cpg
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
180 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
181 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
184 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
187 power-domains = <&cpg>;
201 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
202 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
205 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
208 power-domains = <&cpg>;
222 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
223 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
226 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
229 power-domains = <&cpg>;
243 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
244 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
247 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
250 power-domains = <&cpg>;
262 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
263 resets = <&cpg R9A07G044_RSPI0_RST>;
266 power-domains = <&cpg>;
280 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
281 resets = <&cpg R9A07G044_RSPI1_RST>;
284 power-domains = <&cpg>;
298 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
299 resets = <&cpg R9A07G044_RSPI2_RST>;
302 power-domains = <&cpg>;
320 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
322 power-domains = <&cpg>;
323 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
338 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
340 power-domains = <&cpg>;
341 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
356 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
358 power-domains = <&cpg>;
359 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
374 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
376 power-domains = <&cpg>;
377 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
392 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
394 power-domains = <&cpg>;
395 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
407 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
409 power-domains = <&cpg>;
410 resets = <&cpg R9A07G044_SCI0_RST>;
422 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
424 power-domains = <&cpg>;
425 resets = <&cpg R9A07G044_SCI1_RST>;
443 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
444 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
447 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
449 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
450 <&cpg R9A07G044_CANFD_RSTC_N>;
452 power-domains = <&cpg>;
478 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
480 resets = <&cpg R9A07G044_I2C0_MRST>;
481 power-domains = <&cpg>;
500 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
502 resets = <&cpg R9A07G044_I2C1_MRST>;
503 power-domains = <&cpg>;
522 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
524 resets = <&cpg R9A07G044_I2C2_MRST>;
525 power-domains = <&cpg>;
544 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
546 resets = <&cpg R9A07G044_I2C3_MRST>;
547 power-domains = <&cpg>;
555 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
556 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
558 resets = <&cpg R9A07G044_ADC_PRESETN>,
559 <&cpg R9A07G044_ADC_ADRST_N>;
561 power-domains = <&cpg>;
597 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
598 resets = <&cpg R9A07G044_TSU_PRESETN>;
599 power-domains = <&cpg>;
611 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
612 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
613 resets = <&cpg R9A07G044_SPI_RST>;
614 power-domains = <&cpg>;
620 cpg: clock-controller@11010000 { label
621 compatible = "renesas,r9a07g044-cpg";
652 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
653 power-domains = <&cpg>;
654 resets = <&cpg R9A07G044_GPIO_RSTN>,
655 <&cpg R9A07G044_GPIO_PORT_RESETN>,
656 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
707 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
708 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
710 power-domains = <&cpg>;
711 resets = <&cpg R9A07G044_IA55_RESETN>;
741 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
742 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
743 power-domains = <&cpg>;
744 resets = <&cpg R9A07G044_DMAC_ARESETN>,
745 <&cpg R9A07G044_DMAC_RST_ASYNC>;
759 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
760 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
761 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
763 power-domains = <&cpg>;
764 resets = <&cpg R9A07G044_GPU_RESETN>,
765 <&cpg R9A07G044_GPU_AXI_RESETN>,
766 <&cpg R9A07G044_GPU_ACE_RESETN>;
787 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
788 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
789 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
790 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
792 resets = <&cpg R9A07G044_SDHI0_IXRST>;
793 power-domains = <&cpg>;
803 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
804 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
805 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
806 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
808 resets = <&cpg R9A07G044_SDHI1_IXRST>;
809 power-domains = <&cpg>;
822 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
823 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
824 <&cpg CPG_CORE R9A07G044_CLK_HP>;
826 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
827 power-domains = <&cpg>;
842 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
843 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
844 <&cpg CPG_CORE R9A07G044_CLK_HP>;
846 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
847 power-domains = <&cpg>;
857 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
858 resets = <&cpg R9A07G044_USB_PRESETN>;
859 power-domains = <&cpg>;
868 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
869 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
871 <&cpg R9A07G044_USB_U2H0_HRESETN>;
874 power-domains = <&cpg>;
882 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
883 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
885 <&cpg R9A07G044_USB_U2H1_HRESETN>;
888 power-domains = <&cpg>;
896 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
897 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
899 <&cpg R9A07G044_USB_U2H0_HRESETN>;
903 power-domains = <&cpg>;
911 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
912 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
914 <&cpg R9A07G044_USB_U2H1_HRESETN>;
918 power-domains = <&cpg>;
927 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
928 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
931 power-domains = <&cpg>;
940 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
941 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
944 power-domains = <&cpg>;
956 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
957 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
959 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
963 power-domains = <&cpg>;
971 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
972 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
977 resets = <&cpg R9A07G044_WDT0_PRESETN>;
978 power-domains = <&cpg>;
986 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
987 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
992 resets = <&cpg R9A07G044_WDT1_PRESETN>;
993 power-domains = <&cpg>;
1001 clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
1002 <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
1007 resets = <&cpg R9A07G044_WDT2_PRESETN>;
1008 power-domains = <&cpg>;
1017 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1018 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1019 power-domains = <&cpg>;
1028 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1029 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1030 power-domains = <&cpg>;
1039 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1040 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1041 power-domains = <&cpg>;