Lines Matching full:cpg
9 #include <dt-bindings/clock/r9a07g043-cpg.h>
83 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
115 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
116 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
119 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
122 power-domains = <&cpg>;
136 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
137 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
140 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
143 power-domains = <&cpg>;
157 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
158 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
161 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
164 power-domains = <&cpg>;
178 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
179 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
182 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
185 power-domains = <&cpg>;
197 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
198 resets = <&cpg R9A07G043_RSPI0_RST>;
201 power-domains = <&cpg>;
215 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
216 resets = <&cpg R9A07G043_RSPI1_RST>;
219 power-domains = <&cpg>;
233 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
234 resets = <&cpg R9A07G043_RSPI2_RST>;
237 power-domains = <&cpg>;
256 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
258 power-domains = <&cpg>;
259 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
275 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
277 power-domains = <&cpg>;
278 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
294 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
296 power-domains = <&cpg>;
297 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
313 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
315 power-domains = <&cpg>;
316 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
332 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
334 power-domains = <&cpg>;
335 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
347 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
349 power-domains = <&cpg>;
350 resets = <&cpg R9A07G043_SCI0_RST>;
362 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
364 power-domains = <&cpg>;
365 resets = <&cpg R9A07G043_SCI1_RST>;
383 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
384 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
387 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
389 resets = <&cpg R9A07G043_CANFD_RSTP_N>,
390 <&cpg R9A07G043_CANFD_RSTC_N>;
392 power-domains = <&cpg>;
418 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
420 resets = <&cpg R9A07G043_I2C0_MRST>;
421 power-domains = <&cpg>;
440 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
442 resets = <&cpg R9A07G043_I2C1_MRST>;
443 power-domains = <&cpg>;
462 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
464 resets = <&cpg R9A07G043_I2C2_MRST>;
465 power-domains = <&cpg>;
484 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
486 resets = <&cpg R9A07G043_I2C3_MRST>;
487 power-domains = <&cpg>;
495 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
496 <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
498 resets = <&cpg R9A07G043_ADC_PRESETN>,
499 <&cpg R9A07G043_ADC_ADRST_N>;
501 power-domains = <&cpg>;
519 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
520 resets = <&cpg R9A07G043_TSU_PRESETN>;
521 power-domains = <&cpg>;
532 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
533 <&cpg CPG_MOD R9A07G043_SPI_CLK>;
534 resets = <&cpg R9A07G043_SPI_RST>;
535 power-domains = <&cpg>;
541 cpg: clock-controller@11010000 { label
542 compatible = "renesas,r9a07g043-cpg";
569 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
570 power-domains = <&cpg>;
571 resets = <&cpg R9A07G043_GPIO_RSTN>,
572 <&cpg R9A07G043_GPIO_PORT_RESETN>,
573 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
603 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
604 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
605 power-domains = <&cpg>;
606 resets = <&cpg R9A07G043_DMAC_ARESETN>,
607 <&cpg R9A07G043_DMAC_RST_ASYNC>;
628 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
629 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
630 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
631 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
633 resets = <&cpg R9A07G043_SDHI0_IXRST>;
634 power-domains = <&cpg>;
644 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
645 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
646 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
647 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
649 resets = <&cpg R9A07G043_SDHI1_IXRST>;
650 power-domains = <&cpg>;
663 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
664 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
665 <&cpg CPG_CORE R9A07G043_CLK_HP>;
667 resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
668 power-domains = <&cpg>;
683 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
684 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
685 <&cpg CPG_CORE R9A07G043_CLK_HP>;
687 resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
688 power-domains = <&cpg>;
698 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
699 resets = <&cpg R9A07G043_USB_PRESETN>;
700 power-domains = <&cpg>;
709 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
710 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
712 <&cpg R9A07G043_USB_U2H0_HRESETN>;
715 power-domains = <&cpg>;
723 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
724 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
726 <&cpg R9A07G043_USB_U2H1_HRESETN>;
729 power-domains = <&cpg>;
737 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
738 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
740 <&cpg R9A07G043_USB_U2H0_HRESETN>;
744 power-domains = <&cpg>;
752 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
753 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
755 <&cpg R9A07G043_USB_U2H1_HRESETN>;
759 power-domains = <&cpg>;
768 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
769 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
772 power-domains = <&cpg>;
781 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
782 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
785 power-domains = <&cpg>;
797 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
798 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
800 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>;
804 power-domains = <&cpg>;
812 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
813 <&cpg CPG_MOD R9A07G043_WDT0_CLK>;
818 resets = <&cpg R9A07G043_WDT0_PRESETN>;
819 power-domains = <&cpg>;
827 clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
828 <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
833 resets = <&cpg R9A07G043_WDT2_PRESETN>;
834 power-domains = <&cpg>;
843 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
844 resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
845 power-domains = <&cpg>;
854 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
855 resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
856 power-domains = <&cpg>;
865 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
866 resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
867 power-domains = <&cpg>;