Lines Matching +full:0 +full:x400

18 		#clock-cells = <0>;
20 		clock-frequency = <0>;
25 		#clock-cells = <0>;
27 		clock-frequency = <0>;
33 		#clock-cells = <0>;
34 		clock-frequency = <0>;
40 		#clock-cells = <0>;
42 		clock-frequency = <0>;
45 	cluster0_opp: opp-table-0 {
74 		#size-cells = <0>;
76 		cpu0: cpu@0 {
78 			reg = <0>;
87 		L3_CA55: cache-controller-0 {
90 			cache-size = <0x40000>;
109 			reg = <0 0x10049c00 0 0x400>;
120 			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
123 			#sound-dai-cells = <0>;
130 			reg = <0 0x1004a000 0 0x400>;
141 			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
144 			#sound-dai-cells = <0>;
151 			reg = <0 0x1004a400 0 0x400>;
162 			dmas = <&dmac 0x265f>;
165 			#sound-dai-cells = <0>;
172 			reg = <0 0x1004a800 0 0x400>;
183 			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
186 			#sound-dai-cells = <0>;
192 			reg = <0 0x1004ac00 0 0x400>;
199 			dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
204 			#size-cells = <0>;
210 			reg = <0 0x1004b000 0 0x400>;
217 			dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
222 			#size-cells = <0>;
228 			reg = <0 0x1004b400 0 0x400>;
235 			dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
240 			#size-cells = <0>;
247 			reg = <0 0x1004b800 0 0x400>;
266 			reg = <0 0x1004bc00 0 0x400>;
285 			reg = <0 0x1004c000 0 0x400>;
304 			reg = <0 0x1004c400 0 0x400>;
323 			reg = <0 0x1004c800 0 0x400>;
341 			reg = <0 0x1004d000 0 0x400>;
356 			reg = <0 0x1004d400 0 0x400>;
371 			reg = <0 0x10050000 0 0x8000>;
405 			#size-cells = <0>;
407 			reg = <0 0x10058000 0 0x400>;
427 			#size-cells = <0>;
429 			reg = <0 0x10058400 0 0x400>;
449 			#size-cells = <0>;
451 			reg = <0 0x10058800 0 0x400>;
471 			#size-cells = <0>;
473 			reg = <0 0x10058c00 0 0x400>;
493 			reg = <0 0x10059000 0 0x400>;
505 			#size-cells = <0>;
507 			channel@0 {
508 				reg = <0>;
518 			reg = <0 0x10059400 0 0x400>;
528 			reg = <0 0x10060000 0 0x10000>,
529 			      <0 0x20000000 0 0x10000000>,
530 			      <0 0x10070000 0 0x10000>;
537 			#size-cells = <0>;
543 			reg = <0 0x11010000 0 0x10000>;
548 			#power-domain-cells = <0>;
553 			reg = <0 0x11020000 0 0x10000>;
565 			reg = <0 0x11030000 0 0x10000>;
568 			gpio-ranges = <&pinctrl 0 0 152>;
579 			reg = <0 0x11820000 0 0x10000>,
580 			      <0 0x11830000 0 0x10000>;
615 			#address-cells = <0>;
617 			reg = <0x0 0x11900000 0 0x40000>,
618 			      <0x0 0x11940000 0 0x60000>;
625 			reg = <0x0 0x11c00000 0 0x10000>;
641 			reg = <0x0 0x11c10000 0 0x10000>;
657 			reg = <0 0x11c20000 0 0x10000>;
670 			#size-cells = <0>;
677 			reg = <0 0x11c30000 0 0x10000>;
690 			#size-cells = <0>;
697 			reg = <0 0x11c40000 0 0x10000>;
707 			reg = <0 0x11c50000 0 0x100>;
711 			resets = <&phyrst 0>,
721 			reg = <0 0x11c70000 0 0x100>;
735 			reg = <0 0x11c50100 0 0x100>;
739 			resets = <&phyrst 0>,
750 			reg = <0 0x11c70100 0 0x100>;
766 			reg = <0 0x11c50200 0 0x700>;
770 			resets = <&phyrst 0>;
779 			reg = <0 0x11c70200 0 0x700>;
792 			reg = <0 0x11c60000 0 0x10000>;
799 			resets = <&phyrst 0>,
811 			reg = <0 0x12800800 0 0x400>;
826 			reg = <0 0x12800400 0 0x400>;
841 			reg = <0x0 0x12801000 0x0 0x400>;
852 			reg = <0x0 0x12801400 0x0 0x400>;
863 			reg = <0x0 0x12801800 0x0 0x400>;
876 			thermal-sensors = <&tsu 0>;
882 					cooling-device = <&cpu0 0 2>;