Lines Matching +full:rx +full:- +full:internal +full:- +full:delay

1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu-map {
60 compatible = "arm,cortex-a55";
63 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
64 next-level-cache = <&L3_CA55_0>;
65 enable-method = "psci";
66 cpu-idle-states = <&CPU_SLEEP_0>;
71 compatible = "arm,cortex-a55";
74 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
75 next-level-cache = <&L3_CA55_0>;
76 enable-method = "psci";
77 cpu-idle-states = <&CPU_SLEEP_0>;
82 compatible = "arm,cortex-a55";
85 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
86 next-level-cache = <&L3_CA55_1>;
87 enable-method = "psci";
88 cpu-idle-states = <&CPU_SLEEP_0>;
93 compatible = "arm,cortex-a55";
96 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
97 next-level-cache = <&L3_CA55_1>;
98 enable-method = "psci";
99 cpu-idle-states = <&CPU_SLEEP_0>;
104 compatible = "arm,cortex-a55";
107 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
108 next-level-cache = <&L3_CA55_2>;
109 enable-method = "psci";
110 cpu-idle-states = <&CPU_SLEEP_0>;
115 compatible = "arm,cortex-a55";
118 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
119 next-level-cache = <&L3_CA55_2>;
120 enable-method = "psci";
121 cpu-idle-states = <&CPU_SLEEP_0>;
126 compatible = "arm,cortex-a55";
129 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
130 next-level-cache = <&L3_CA55_3>;
131 enable-method = "psci";
132 cpu-idle-states = <&CPU_SLEEP_0>;
137 compatible = "arm,cortex-a55";
140 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
141 next-level-cache = <&L3_CA55_3>;
142 enable-method = "psci";
143 cpu-idle-states = <&CPU_SLEEP_0>;
147 L3_CA55_0: cache-controller-0 {
149 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
150 cache-unified;
151 cache-level = <3>;
154 L3_CA55_1: cache-controller-1 {
156 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
157 cache-unified;
158 cache-level = <3>;
161 L3_CA55_2: cache-controller-2 {
163 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
164 cache-unified;
165 cache-level = <3>;
168 L3_CA55_3: cache-controller-3 {
170 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
171 cache-unified;
172 cache-level = <3>;
175 idle-states {
176 entry-method = "psci";
178 CPU_SLEEP_0: cpu-sleep-0 {
179 compatible = "arm,idle-state";
180 arm,psci-suspend-param = <0x0010000>;
181 local-timer-stop;
182 entry-latency-us = <400>;
183 exit-latency-us = <500>;
184 min-residency-us = <4000>;
190 compatible = "fixed-clock";
191 #clock-cells = <0>;
193 clock-frequency = <0>;
197 compatible = "fixed-clock";
198 #clock-cells = <0>;
200 clock-frequency = <0>;
204 compatible = "arm,cortex-a55-pmu";
205 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
209 compatible = "arm,psci-1.0", "arm,psci-0.2";
213 /* External SCIF clock - to be overridden by boards that provide it */
215 compatible = "fixed-clock";
216 #clock-cells = <0>;
217 clock-frequency = <0>;
221 compatible = "simple-bus";
222 interrupt-parent = <&gic>;
223 #address-cells = <2>;
224 #size-cells = <2>;
228 compatible = "renesas,r8a779f0-wdt",
229 "renesas,rcar-gen4-wdt";
233 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
239 compatible = "renesas,pfc-r8a779f0";
245 compatible = "renesas,gpio-r8a779f0",
246 "renesas,rcar-gen4-gpio";
250 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 gpio-ranges = <&pfc 0 0 21>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
260 compatible = "renesas,gpio-r8a779f0",
261 "renesas,rcar-gen4-gpio";
265 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
267 gpio-controller;
268 #gpio-cells = <2>;
269 gpio-ranges = <&pfc 0 32 25>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
275 compatible = "renesas,gpio-r8a779f0",
276 "renesas,rcar-gen4-gpio";
280 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
282 gpio-controller;
283 #gpio-cells = <2>;
284 gpio-ranges = <&pfc 0 64 17>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
290 compatible = "renesas,gpio-r8a779f0",
291 "renesas,rcar-gen4-gpio";
295 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 gpio-ranges = <&pfc 0 96 19>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
305 compatible = "renesas,r8a779f0-cmt0",
306 "renesas,rcar-gen4-cmt0";
311 clock-names = "fck";
312 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
318 compatible = "renesas,r8a779f0-cmt1",
319 "renesas,rcar-gen4-cmt1";
330 clock-names = "fck";
331 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
337 compatible = "renesas,r8a779f0-cmt1",
338 "renesas,rcar-gen4-cmt1";
349 clock-names = "fck";
350 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
356 compatible = "renesas,r8a779f0-cmt1",
357 "renesas,rcar-gen4-cmt1";
368 clock-names = "fck";
369 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
374 cpg: clock-controller@e6150000 {
375 compatible = "renesas,r8a779f0-cpg-mssr";
378 clock-names = "extal", "extalr";
379 #clock-cells = <2>;
380 #power-domain-cells = <0>;
381 #reset-cells = <1>;
384 rst: reset-controller@e6160000 {
385 compatible = "renesas,r8a779f0-rst";
389 sysc: system-controller@e6180000 {
390 compatible = "renesas,r8a779f0-sysc";
392 #power-domain-cells = <1>;
396 compatible = "renesas,r8a779f0-thermal";
402 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
404 #thermal-sensor-cells = <1>;
408 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
414 clock-names = "fck";
415 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
421 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
427 clock-names = "fck";
428 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
434 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
440 clock-names = "fck";
441 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
447 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
453 clock-names = "fck";
454 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
460 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
466 clock-names = "fck";
467 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
473 compatible = "renesas,i2c-r8a779f0",
474 "renesas,rcar-gen4-i2c";
478 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
482 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay-ns = <110>;
484 #address-cells = <1>;
485 #size-cells = <0>;
490 compatible = "renesas,i2c-r8a779f0",
491 "renesas,rcar-gen4-i2c";
495 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
499 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay-ns = <110>;
501 #address-cells = <1>;
502 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a779f0",
508 "renesas,rcar-gen4-i2c";
512 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
516 dma-names = "tx", "rx", "tx", "rx";
517 i2c-scl-internal-delay-ns = <110>;
518 #address-cells = <1>;
519 #size-cells = <0>;
524 compatible = "renesas,i2c-r8a779f0",
525 "renesas,rcar-gen4-i2c";
529 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
533 dma-names = "tx", "rx", "tx", "rx";
534 i2c-scl-internal-delay-ns = <110>;
535 #address-cells = <1>;
536 #size-cells = <0>;
541 compatible = "renesas,i2c-r8a779f0",
542 "renesas,rcar-gen4-i2c";
546 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
550 dma-names = "tx", "rx", "tx", "rx";
551 i2c-scl-internal-delay-ns = <110>;
552 #address-cells = <1>;
553 #size-cells = <0>;
558 compatible = "renesas,i2c-r8a779f0",
559 "renesas,rcar-gen4-i2c";
563 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
567 dma-names = "tx", "rx", "tx", "rx";
568 i2c-scl-internal-delay-ns = <110>;
569 #address-cells = <1>;
570 #size-cells = <0>;
575 compatible = "renesas,hscif-r8a779f0",
576 "renesas,rcar-gen4-hscif", "renesas,hscif";
582 clock-names = "fck", "brg_int", "scif_clk";
585 dma-names = "tx", "rx", "tx", "rx";
586 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
592 compatible = "renesas,hscif-r8a779f0",
593 "renesas,rcar-gen4-hscif", "renesas,hscif";
599 clock-names = "fck", "brg_int", "scif_clk";
602 dma-names = "tx", "rx", "tx", "rx";
603 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
609 compatible = "renesas,hscif-r8a779f0",
610 "renesas,rcar-gen4-hscif", "renesas,hscif";
616 clock-names = "fck", "brg_int", "scif_clk";
619 dma-names = "tx", "rx", "tx", "rx";
620 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
626 compatible = "renesas,hscif-r8a779f0",
627 "renesas,rcar-gen4-hscif", "renesas,hscif";
633 clock-names = "fck", "brg_int", "scif_clk";
636 dma-names = "tx", "rx", "tx", "rx";
637 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
643 compatible = "renesas,r8a779f0-ufs";
647 clock-names = "fck", "ref_clk";
648 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
649 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
655 compatible = "renesas,scif-r8a779f0",
656 "renesas,rcar-gen4-scif", "renesas,scif";
662 clock-names = "fck", "brg_int", "scif_clk";
665 dma-names = "tx", "rx", "tx", "rx";
666 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
672 compatible = "renesas,scif-r8a779f0",
673 "renesas,rcar-gen4-scif", "renesas,scif";
679 clock-names = "fck", "brg_int", "scif_clk";
682 dma-names = "tx", "rx", "tx", "rx";
683 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
689 compatible = "renesas,scif-r8a779f0",
690 "renesas,rcar-gen4-scif", "renesas,scif";
696 clock-names = "fck", "brg_int", "scif_clk";
699 dma-names = "tx", "rx", "tx", "rx";
700 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
706 compatible = "renesas,scif-r8a779f0",
707 "renesas,rcar-gen4-scif", "renesas,scif";
713 clock-names = "fck", "brg_int", "scif_clk";
716 dma-names = "tx", "rx", "tx", "rx";
717 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
723 compatible = "renesas,msiof-r8a779f0",
724 "renesas,rcar-gen4-msiof";
730 dma-names = "tx", "rx", "tx", "rx";
731 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
733 #address-cells = <1>;
734 #size-cells = <0>;
739 compatible = "renesas,msiof-r8a779f0",
740 "renesas,rcar-gen4-msiof";
746 dma-names = "tx", "rx", "tx", "rx";
747 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
749 #address-cells = <1>;
750 #size-cells = <0>;
755 compatible = "renesas,msiof-r8a779f0",
756 "renesas,rcar-gen4-msiof";
762 dma-names = "tx", "rx", "tx", "rx";
763 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
765 #address-cells = <1>;
766 #size-cells = <0>;
771 compatible = "renesas,msiof-r8a779f0",
772 "renesas,rcar-gen4-msiof";
778 dma-names = "tx", "rx", "tx", "rx";
779 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
781 #address-cells = <1>;
782 #size-cells = <0>;
786 dmac0: dma-controller@e7350000 {
787 compatible = "renesas,dmac-r8a779f0",
788 "renesas,rcar-gen4-dmac";
808 interrupt-names = "error",
814 clock-names = "fck";
815 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
817 #dma-cells = <1>;
818 dma-channels = <16>;
829 dmac1: dma-controller@e7351000 {
830 compatible = "renesas,dmac-r8a779f0",
831 "renesas,rcar-gen4-dmac";
851 interrupt-names = "error",
857 clock-names = "fck";
858 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
860 #dma-cells = <1>;
861 dma-channels = <16>;
873 compatible = "renesas,sdhi-r8a779f0",
874 "renesas,rcar-gen4-sdhi";
878 clock-names = "core", "clkh";
879 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
881 max-frequency = <200000000>;
886 compatible = "renesas,ipmmu-r8a779f0",
887 "renesas,rcar-gen4-ipmmu-vmsa";
889 renesas,ipmmu-main = <&ipmmu_mm 10>;
890 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
891 #iommu-cells = <1>;
895 compatible = "renesas,ipmmu-r8a779f0",
896 "renesas,rcar-gen4-ipmmu-vmsa";
898 renesas,ipmmu-main = <&ipmmu_mm 19>;
899 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
900 #iommu-cells = <1>;
904 compatible = "renesas,ipmmu-r8a779f0",
905 "renesas,rcar-gen4-ipmmu-vmsa";
907 renesas,ipmmu-main = <&ipmmu_mm 0>;
908 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
909 #iommu-cells = <1>;
913 compatible = "renesas,ipmmu-r8a779f0",
914 "renesas,rcar-gen4-ipmmu-vmsa";
916 renesas,ipmmu-main = <&ipmmu_mm 2>;
917 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
918 #iommu-cells = <1>;
922 compatible = "renesas,ipmmu-r8a779f0",
923 "renesas,rcar-gen4-ipmmu-vmsa";
927 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
928 #iommu-cells = <1>;
931 gic: interrupt-controller@f1000000 {
932 compatible = "arm,gic-v3";
933 #interrupt-cells = <3>;
934 #address-cells = <0>;
935 interrupt-controller;
948 thermal-zones {
949 sensor_thermal1: sensor1-thermal {
950 polling-delay-passive = <250>;
951 polling-delay = <1000>;
952 thermal-sensors = <&tsc 0>;
955 sensor1_crit: sensor1-crit {
963 sensor_thermal2: sensor2-thermal {
964 polling-delay-passive = <250>;
965 polling-delay = <1000>;
966 thermal-sensors = <&tsc 1>;
969 sensor2_crit: sensor2-crit {
977 sensor_thermal3: sensor3-thermal {
978 polling-delay-passive = <250>;
979 polling-delay = <1000>;
980 thermal-sensors = <&tsc 2>;
983 sensor3_crit: sensor3-crit {
993 compatible = "arm,armv8-timer";
994 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1000 ufs30_clk: ufs30-clk {
1001 compatible = "fixed-clock";
1002 #clock-cells = <0>;
1004 clock-frequency = <0>;