Lines Matching +full:0 +full:xe6130000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #size-cells = <0>;
28 a76_0: cpu@0 {
30 reg = <0>;
37 L3_CA76_0: cache-controller-0 {
47 #clock-cells = <0>;
49 clock-frequency = <0>;
54 #clock-cells = <0>;
56 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
81 reg = <0 0xe6020000 0 0x0c>;
91 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
92 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
93 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
94 <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
95 <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
101 reg = <0 0xe6058180 0 0x54>;
108 gpio-ranges = <&pfc 0 0 28>;
116 reg = <0 0xe6050180 0 0x54>;
123 gpio-ranges = <&pfc 0 32 31>;
131 reg = <0 0xe6050980 0 0x54>;
138 gpio-ranges = <&pfc 0 64 25>;
146 reg = <0 0xe6058980 0 0x54>;
153 gpio-ranges = <&pfc 0 96 17>;
161 reg = <0 0xe6060180 0 0x54>;
168 gpio-ranges = <&pfc 0 128 27>;
176 reg = <0 0xe6060980 0 0x54>;
183 gpio-ranges = <&pfc 0 160 21>;
191 reg = <0 0xe6068180 0 0x54>;
198 gpio-ranges = <&pfc 0 192 21>;
206 reg = <0 0xe6068980 0 0x54>;
213 gpio-ranges = <&pfc 0 224 21>;
221 reg = <0 0xe6069180 0 0x54>;
228 gpio-ranges = <&pfc 0 256 21>;
236 reg = <0 0xe6069980 0 0x54>;
243 gpio-ranges = <&pfc 0 288 21>;
251 reg = <0 0xe60f0000 0 0x1004>;
264 reg = <0 0xe6130000 0 0x1004>;
283 reg = <0 0xe6140000 0 0x1004>;
302 reg = <0 0xe6148000 0 0x1004>;
320 reg = <0 0xe6150000 0 0x4000>;
324 #power-domain-cells = <0>;
330 reg = <0 0xe6160000 0 0x4000>;
335 reg = <0 0xe6180000 0 0x4000>;
341 reg = <0 0xe6190000 0 0x200>,
342 <0 0xe6198000 0 0x200>,
343 <0 0xe61a0000 0 0x200>,
344 <0 0xe61a8000 0 0x200>,
345 <0 0xe61b0000 0 0x200>;
356 reg = <0 0xe61c0000 0 0x200>;
357 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
369 reg = <0 0xe61e0000 0 0x30>;
382 reg = <0 0xe6fc0000 0 0x30>;
395 reg = <0 0xe6fd0000 0 0x30>;
408 reg = <0 0xe6fe0000 0 0x30>;
421 reg = <0 0xffc00000 0 0x30>;
435 reg = <0 0xe6500000 0 0x40>;
440 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
444 #size-cells = <0>;
451 reg = <0 0xe6508000 0 0x40>;
456 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
460 #size-cells = <0>;
467 reg = <0 0xe6510000 0 0x40>;
472 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
476 #size-cells = <0>;
483 reg = <0 0xe66d0000 0 0x40>;
488 dmas = <&dmac1 0x97>, <&dmac1 0x96>;
492 #size-cells = <0>;
499 reg = <0 0xe66d8000 0 0x40>;
504 dmas = <&dmac1 0x99>, <&dmac1 0x98>;
508 #size-cells = <0>;
515 reg = <0 0xe66e0000 0 0x40>;
520 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
524 #size-cells = <0>;
531 reg = <0 0xe66e8000 0 0x40>;
536 dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
540 #size-cells = <0>;
547 reg = <0 0xe6540000 0 0x60>;
553 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
563 reg = <0 0xe6550000 0 0x60>;
569 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
579 reg = <0 0xe6560000 0 0x60>;
585 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
595 reg = <0 0xe66a0000 0 0x60>;
601 dmas = <&dmac1 0x37>, <&dmac1 0x36>;
610 reg = <0 0xe6660000 0 0x8000>;
660 reg = <0 0xe6800000 0 0x800>;
698 rx-internal-delay-ps = <0>;
699 tx-internal-delay-ps = <0>;
701 #size-cells = <0>;
708 reg = <0 0xe6810000 0 0x800>;
746 rx-internal-delay-ps = <0>;
747 tx-internal-delay-ps = <0>;
749 #size-cells = <0>;
756 reg = <0 0xe6820000 0 0x1000>;
794 rx-internal-delay-ps = <0>;
795 tx-internal-delay-ps = <0>;
797 #size-cells = <0>;
804 reg = <0 0xe6830000 0 0x1000>;
842 rx-internal-delay-ps = <0>;
843 tx-internal-delay-ps = <0>;
845 #size-cells = <0>;
852 reg = <0 0xe6840000 0 0x1000>;
890 rx-internal-delay-ps = <0>;
891 tx-internal-delay-ps = <0>;
893 #size-cells = <0>;
900 reg = <0 0xe6850000 0 0x1000>;
938 rx-internal-delay-ps = <0>;
939 tx-internal-delay-ps = <0>;
941 #size-cells = <0>;
948 reg = <0 0xe6e60000 0 64>;
954 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
964 reg = <0 0xe6e68000 0 64>;
970 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
980 reg = <0 0xe6c50000 0 64>;
986 dmas = <&dmac1 0x57>, <&dmac1 0x56>;
996 reg = <0 0xe6c40000 0 64>;
1002 dmas = <&dmac1 0x59>, <&dmac1 0x58>;
1011 reg = <0 0xe6e80000 0 0x148>;
1023 reg = <0 0xe6e90000 0 0x0064>;
1028 dmas = <&dmac1 0x41>, <&dmac1 0x40>;
1031 #size-cells = <0>;
1038 reg = <0 0xe6ea0000 0 0x0064>;
1043 dmas = <&dmac1 0x43>, <&dmac1 0x42>;
1046 #size-cells = <0>;
1053 reg = <0 0xe6c00000 0 0x0064>;
1058 dmas = <&dmac1 0x45>, <&dmac1 0x44>;
1061 #size-cells = <0>;
1068 reg = <0 0xe6c10000 0 0x0064>;
1073 dmas = <&dmac1 0x47>, <&dmac1 0x46>;
1076 #size-cells = <0>;
1083 reg = <0 0xe6c20000 0 0x0064>;
1088 dmas = <&dmac1 0x49>, <&dmac1 0x48>;
1091 #size-cells = <0>;
1098 reg = <0 0xe6c28000 0 0x0064>;
1103 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
1106 #size-cells = <0>;
1112 reg = <0 0xe6ef0000 0 0x1000>;
1117 renesas,id = <0>;
1122 #size-cells = <0>;
1126 #size-cells = <0>;
1130 vin00isp0: endpoint@0 {
1131 reg = <0>;
1140 reg = <0 0xe6ef1000 0 0x1000>;
1150 #size-cells = <0>;
1154 #size-cells = <0>;
1158 vin01isp0: endpoint@0 {
1159 reg = <0>;
1168 reg = <0 0xe6ef2000 0 0x1000>;
1178 #size-cells = <0>;
1182 #size-cells = <0>;
1186 vin02isp0: endpoint@0 {
1187 reg = <0>;
1196 reg = <0 0xe6ef3000 0 0x1000>;
1206 #size-cells = <0>;
1210 #size-cells = <0>;
1214 vin03isp0: endpoint@0 {
1215 reg = <0>;
1224 reg = <0 0xe6ef4000 0 0x1000>;
1234 #size-cells = <0>;
1238 #size-cells = <0>;
1242 vin04isp0: endpoint@0 {
1243 reg = <0>;
1252 reg = <0 0xe6ef5000 0 0x1000>;
1262 #size-cells = <0>;
1266 #size-cells = <0>;
1270 vin05isp0: endpoint@0 {
1271 reg = <0>;
1280 reg = <0 0xe6ef6000 0 0x1000>;
1290 #size-cells = <0>;
1294 #size-cells = <0>;
1298 vin06isp0: endpoint@0 {
1299 reg = <0>;
1308 reg = <0 0xe6ef7000 0 0x1000>;
1318 #size-cells = <0>;
1322 #size-cells = <0>;
1326 vin07isp0: endpoint@0 {
1327 reg = <0>;
1336 reg = <0 0xe6ef8000 0 0x1000>;
1346 #size-cells = <0>;
1350 #size-cells = <0>;
1364 reg = <0 0xe6ef9000 0 0x1000>;
1374 #size-cells = <0>;
1378 #size-cells = <0>;
1392 reg = <0 0xe6efa000 0 0x1000>;
1402 #size-cells = <0>;
1406 #size-cells = <0>;
1420 reg = <0 0xe6efb000 0 0x1000>;
1430 #size-cells = <0>;
1434 #size-cells = <0>;
1448 reg = <0 0xe6efc000 0 0x1000>;
1458 #size-cells = <0>;
1462 #size-cells = <0>;
1476 reg = <0 0xe6efd000 0 0x1000>;
1486 #size-cells = <0>;
1490 #size-cells = <0>;
1504 reg = <0 0xe6efe000 0 0x1000>;
1514 #size-cells = <0>;
1518 #size-cells = <0>;
1532 reg = <0 0xe6eff000 0 0x1000>;
1542 #size-cells = <0>;
1546 #size-cells = <0>;
1560 reg = <0 0xe6ed0000 0 0x1000>;
1570 #size-cells = <0>;
1574 #size-cells = <0>;
1588 reg = <0 0xe6ed1000 0 0x1000>;
1598 #size-cells = <0>;
1602 #size-cells = <0>;
1616 reg = <0 0xe6ed2000 0 0x1000>;
1626 #size-cells = <0>;
1630 #size-cells = <0>;
1644 reg = <0 0xe6ed3000 0 0x1000>;
1654 #size-cells = <0>;
1658 #size-cells = <0>;
1672 reg = <0 0xe6ed4000 0 0x1000>;
1682 #size-cells = <0>;
1686 #size-cells = <0>;
1700 reg = <0 0xe6ed5000 0 0x1000>;
1710 #size-cells = <0>;
1714 #size-cells = <0>;
1728 reg = <0 0xe6ed6000 0 0x1000>;
1738 #size-cells = <0>;
1742 #size-cells = <0>;
1756 reg = <0 0xe6ed7000 0 0x1000>;
1766 #size-cells = <0>;
1770 #size-cells = <0>;
1784 reg = <0 0xe6ed8000 0 0x1000>;
1794 #size-cells = <0>;
1798 #size-cells = <0>;
1812 reg = <0 0xe6ed9000 0 0x1000>;
1822 #size-cells = <0>;
1826 #size-cells = <0>;
1840 reg = <0 0xe6eda000 0 0x1000>;
1850 #size-cells = <0>;
1854 #size-cells = <0>;
1868 reg = <0 0xe6edb000 0 0x1000>;
1878 #size-cells = <0>;
1882 #size-cells = <0>;
1896 reg = <0 0xe6edc000 0 0x1000>;
1906 #size-cells = <0>;
1910 #size-cells = <0>;
1924 reg = <0 0xe6edd000 0 0x1000>;
1934 #size-cells = <0>;
1938 #size-cells = <0>;
1952 reg = <0 0xe6ede000 0 0x1000>;
1962 #size-cells = <0>;
1966 #size-cells = <0>;
1980 reg = <0 0xe6edf000 0 0x1000>;
1990 #size-cells = <0>;
1994 #size-cells = <0>;
2009 reg = <0 0xe7350000 0 0x1000>,
2010 <0 0xe7300000 0 0x10000>;
2044 reg = <0 0xe7351000 0 0x1000>,
2045 <0 0xe7310000 0 0x10000>;
2069 reg = <0 0xee140000 0 0x2000>;
2083 reg = <0 0xee200000 0 0x200>,
2084 <0 0x08000000 0 0x04000000>,
2085 <0 0xee208000 0 0x100>;
2092 #size-cells = <0>;
2099 reg = <0 0xee480000 0 0x20000>;
2108 reg = <0 0xee4c0000 0 0x20000>;
2117 reg = <0 0xeed00000 0 0x20000>;
2118 renesas,ipmmu-main = <&ipmmu_mm 0>;
2126 reg = <0 0xeed40000 0 0x20000>;
2135 reg = <0 0xeed80000 0 0x20000>;
2144 reg = <0 0xeedc0000 0 0x20000>;
2153 reg = <0 0xeee80000 0 0x20000>;
2162 reg = <0 0xeeec0000 0 0x20000>;
2171 reg = <0 0xeee00000 0 0x20000>;
2180 reg = <0 0xeef00000 0 0x20000>;
2189 reg = <0 0xeef40000 0 0x20000>;
2198 reg = <0 0xeefc0000 0 0x20000>;
2208 #address-cells = <0>;
2210 reg = <0x0 0xf1000000 0 0x20000>,
2211 <0x0 0xf1060000 0 0x110000>;
2218 reg = <0 0xfea10000 0 0x200>;
2226 reg = <0 0xfea11000 0 0x200>;
2234 reg = <0 0xfea20000 0 0x5000>;
2245 reg = <0 0xfea28000 0 0x5000>;
2256 reg = <0 0xfeaa0000 0 0x10000>;
2265 #size-cells = <0>;
2267 port@0 {
2268 reg = <0>;
2282 reg = <0 0xfeab0000 0 0x10000>;
2291 #size-cells = <0>;
2293 port@0 {
2294 reg = <0>;
2308 reg = <0 0xfed60000 0 0x10000>;
2317 #size-cells = <0>;
2319 port@0 {
2320 reg = <0>;
2334 reg = <0 0xfed70000 0 0x10000>;
2343 #size-cells = <0>;
2345 port@0 {
2346 reg = <0>;
2360 reg = <0 0xfeb00000 0 0x40000>;
2364 clock-names = "du.0";
2367 reset-names = "du.0";
2368 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2374 #size-cells = <0>;
2376 port@0 {
2377 reg = <0>;
2394 reg = <0 0xfed00000 0 0x10000>;
2403 #size-cells = <0>;
2405 port@0 {
2407 #size-cells = <0>;
2409 reg = <0>;
2411 isp0csi40: endpoint@0 {
2412 reg = <0>;
2477 reg = <0 0xfed20000 0 0x10000>;
2486 #size-cells = <0>;
2488 port@0 {
2490 #size-cells = <0>;
2492 reg = <0>;
2560 reg = <0 0xfed30000 0 0x10000>;
2569 #size-cells = <0>;
2571 port@0 {
2573 #size-cells = <0>;
2575 reg = <0>;
2577 isp2csi42: endpoint@0 {
2578 reg = <0>;
2643 reg = <0 0xfed40000 0 0x10000>;
2652 #size-cells = <0>;
2654 port@0 {
2656 #size-cells = <0>;
2658 reg = <0>;
2726 reg = <0 0xfed80000 0 0x10000>;
2737 #size-cells = <0>;
2739 port@0 {
2740 reg = <0>;
2754 reg = <0 0xfed90000 0 0x10000>;
2765 #size-cells = <0>;
2767 port@0 {
2768 reg = <0>;
2782 reg = <0 0xfff00044 0 4>;
2790 thermal-sensors = <&tsc 0>;