Lines Matching +full:0 +full:xee000000
25 * The external audio clocks are configured as 0 Hz fixed frequency
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
54 cluster0_opp: opp-table-0 {
96 #size-cells = <0>;
98 a57_0: cpu@0 {
100 reg = <0x0>;
114 reg = <0x1>;
124 L2_CA57: cache-controller-0 {
134 CPU_SLEEP_0: cpu-sleep-0 {
136 arm,psci-suspend-param = <0x0010000>;
147 #clock-cells = <0>;
149 clock-frequency = <0>;
154 #clock-cells = <0>;
156 clock-frequency = <0>;
162 #clock-cells = <0>;
163 clock-frequency = <0>;
182 #clock-cells = <0>;
183 clock-frequency = <0>;
196 reg = <0 0xe6020000 0 0x0c>;
207 reg = <0 0xe6050000 0 0x50>;
211 gpio-ranges = <&pfc 0 0 16>;
222 reg = <0 0xe6051000 0 0x50>;
226 gpio-ranges = <&pfc 0 32 29>;
237 reg = <0 0xe6052000 0 0x50>;
241 gpio-ranges = <&pfc 0 64 15>;
252 reg = <0 0xe6053000 0 0x50>;
256 gpio-ranges = <&pfc 0 96 16>;
267 reg = <0 0xe6054000 0 0x50>;
271 gpio-ranges = <&pfc 0 128 18>;
282 reg = <0 0xe6055000 0 0x50>;
286 gpio-ranges = <&pfc 0 160 26>;
297 reg = <0 0xe6055400 0 0x50>;
301 gpio-ranges = <&pfc 0 192 32>;
312 reg = <0 0xe6055800 0 0x50>;
316 gpio-ranges = <&pfc 0 224 4>;
326 reg = <0 0xe6060000 0 0x50c>;
332 reg = <0 0xe60f0000 0 0x1004>;
345 reg = <0 0xe6130000 0 0x1004>;
364 reg = <0 0xe6140000 0 0x1004>;
383 reg = <0 0xe6148000 0 0x1004>;
401 reg = <0 0xe6150000 0 0x1000>;
405 #power-domain-cells = <0>;
411 reg = <0 0xe6160000 0 0x0200>;
416 reg = <0 0xe6180000 0 0x0400>;
422 reg = <0 0xe6198000 0 0x100>,
423 <0 0xe61a0000 0 0x100>,
424 <0 0xe61a8000 0 0x100>;
438 reg = <0 0xe61c0000 0 0x200>;
439 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
452 reg = <0 0xe61e0000 0 0x30>;
465 reg = <0 0xe6fc0000 0 0x30>;
478 reg = <0 0xe6fd0000 0 0x30>;
491 reg = <0 0xe6fe0000 0 0x30>;
504 reg = <0 0xffc00000 0 0x30>;
517 #size-cells = <0>;
520 reg = <0 0xe6500000 0 0x40>;
525 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
526 <&dmac2 0x91>, <&dmac2 0x90>;
534 #size-cells = <0>;
537 reg = <0 0xe6508000 0 0x40>;
542 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
543 <&dmac2 0x93>, <&dmac2 0x92>;
551 #size-cells = <0>;
554 reg = <0 0xe6510000 0 0x40>;
559 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
560 <&dmac2 0x95>, <&dmac2 0x94>;
568 #size-cells = <0>;
571 reg = <0 0xe66d0000 0 0x40>;
576 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
584 #size-cells = <0>;
587 reg = <0 0xe66d8000 0 0x40>;
592 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
600 #size-cells = <0>;
603 reg = <0 0xe66e0000 0 0x40>;
608 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
616 #size-cells = <0>;
619 reg = <0 0xe66e8000 0 0x40>;
624 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
632 #size-cells = <0>;
636 reg = <0 0xe60b0000 0 0x425>;
641 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
650 reg = <0 0xe6540000 0 0x60>;
656 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
657 <&dmac2 0x31>, <&dmac2 0x30>;
668 reg = <0 0xe6550000 0 0x60>;
674 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
675 <&dmac2 0x33>, <&dmac2 0x32>;
686 reg = <0 0xe6560000 0 0x60>;
692 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
693 <&dmac2 0x35>, <&dmac2 0x34>;
704 reg = <0 0xe66a0000 0 0x60>;
710 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
721 reg = <0 0xe66b0000 0 0x60>;
727 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
737 reg = <0 0xe6590000 0 0x200>;
740 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
741 <&usb_dmac1 0>, <&usb_dmac1 1>;
754 reg = <0 0xe65a0000 0 0x100>;
768 reg = <0 0xe65b0000 0 0x100>;
782 reg = <0 0xe65ee000 0 0x90>;
788 #phy-cells = <0>;
795 reg = <0x0 0xe6601000 0 0x1000>;
804 reg = <0 0xe6700000 0 0x10000>;
833 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
846 reg = <0 0xe7300000 0 0x10000>;
875 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
888 reg = <0 0xe7310000 0 0x10000>;
929 reg = <0 0xe6740000 0 0x1000>;
930 renesas,ipmmu-main = <&ipmmu_mm 0>;
937 reg = <0 0xe7740000 0 0x1000>;
945 reg = <0 0xe6570000 0 0x1000>;
953 reg = <0 0xe67b0000 0 0x1000>;
962 reg = <0 0xec670000 0 0x1000>;
970 reg = <0 0xfd800000 0 0x1000>;
978 reg = <0 0xffc80000 0 0x1000>;
986 reg = <0 0xfe6b0000 0 0x1000>;
994 reg = <0 0xfebd0000 0 0x1000>;
1002 reg = <0 0xfe990000 0 0x1000>;
1011 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1049 rx-internal-delay-ps = <0>;
1050 tx-internal-delay-ps = <0>;
1053 #size-cells = <0>;
1060 reg = <0 0xe6c30000 0 0x1000>;
1076 reg = <0 0xe6c38000 0 0x1000>;
1092 reg = <0 0xe66c0000 0 0x8000>;
1117 reg = <0 0xe6e30000 0 8>;
1127 reg = <0 0xe6e31000 0 8>;
1137 reg = <0 0xe6e32000 0 8>;
1147 reg = <0 0xe6e33000 0 8>;
1157 reg = <0 0xe6e34000 0 8>;
1167 reg = <0 0xe6e35000 0 8>;
1177 reg = <0 0xe6e36000 0 8>;
1188 reg = <0 0xe6e60000 0 64>;
1194 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1195 <&dmac2 0x51>, <&dmac2 0x50>;
1205 reg = <0 0xe6e68000 0 64>;
1211 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1212 <&dmac2 0x53>, <&dmac2 0x52>;
1222 reg = <0 0xe6e88000 0 64>;
1228 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1229 <&dmac2 0x13>, <&dmac2 0x12>;
1239 reg = <0 0xe6c50000 0 64>;
1245 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1255 reg = <0 0xe6c40000 0 64>;
1261 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1271 reg = <0 0xe6f30000 0 64>;
1277 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1278 <&dmac2 0x5b>, <&dmac2 0x5a>;
1287 reg = <0 0xe6e80000 0 0x148>;
1299 reg = <0 0xe6e90000 0 0x0064>;
1302 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1303 <&dmac2 0x41>, <&dmac2 0x40>;
1308 #size-cells = <0>;
1315 reg = <0 0xe6ea0000 0 0x0064>;
1318 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1319 <&dmac2 0x43>, <&dmac2 0x42>;
1324 #size-cells = <0>;
1331 reg = <0 0xe6c00000 0 0x0064>;
1334 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1339 #size-cells = <0>;
1346 reg = <0 0xe6c10000 0 0x0064>;
1349 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1354 #size-cells = <0>;
1360 reg = <0 0xe6ef0000 0 0x1000>;
1365 renesas,id = <0>;
1370 #size-cells = <0>;
1374 #size-cells = <0>;
1378 vin0csi20: endpoint@0 {
1379 reg = <0>;
1392 reg = <0 0xe6ef1000 0 0x1000>;
1402 #size-cells = <0>;
1406 #size-cells = <0>;
1410 vin1csi20: endpoint@0 {
1411 reg = <0>;
1424 reg = <0 0xe6ef2000 0 0x1000>;
1434 #size-cells = <0>;
1438 #size-cells = <0>;
1442 vin2csi20: endpoint@0 {
1443 reg = <0>;
1456 reg = <0 0xe6ef3000 0 0x1000>;
1466 #size-cells = <0>;
1470 #size-cells = <0>;
1474 vin3csi20: endpoint@0 {
1475 reg = <0>;
1488 reg = <0 0xe6ef4000 0 0x1000>;
1498 #size-cells = <0>;
1502 #size-cells = <0>;
1506 vin4csi20: endpoint@0 {
1507 reg = <0>;
1520 reg = <0 0xe6ef5000 0 0x1000>;
1530 #size-cells = <0>;
1534 #size-cells = <0>;
1538 vin5csi20: endpoint@0 {
1539 reg = <0>;
1552 reg = <0 0xe6ef6000 0 0x1000>;
1562 #size-cells = <0>;
1566 #size-cells = <0>;
1570 vin6csi20: endpoint@0 {
1571 reg = <0>;
1584 reg = <0 0xe6ef7000 0 0x1000>;
1594 #size-cells = <0>;
1598 #size-cells = <0>;
1602 vin7csi20: endpoint@0 {
1603 reg = <0>;
1617 reg = <0 0xe6f40000 0 0x84>;
1621 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1632 reg = <0 0xe6f50000 0 0x84>;
1636 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1647 reg = <0 0xe6f60000 0 0x84>;
1651 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1662 reg = <0 0xe6f70000 0 0x84>;
1666 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1677 reg = <0 0xe6f80000 0 0x84>;
1681 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1692 reg = <0 0xe6f90000 0 0x84>;
1696 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1707 reg = <0 0xe6fa0000 0 0x84>;
1711 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1722 reg = <0 0xe6fb0000 0 0x84>;
1726 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1738 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1744 * clkout : #clock-cells = <0>; <&rcar_sound>;
1748 reg = <0 0xec500000 0 0x1000>, /* SCU */
1749 <0 0xec5a0000 0 0x100>, /* ADG */
1750 <0 0xec540000 0 0x1000>, /* SSIU */
1751 <0 0xec541000 0 0x280>, /* SSI */
1752 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1775 "ssi.1", "ssi.0",
1778 "src.1", "src.0",
1779 "mix.1", "mix.0",
1780 "ctu.1", "ctu.0",
1781 "dvc.0", "dvc.1",
1793 "ssi.1", "ssi.0";
1797 dvc0: dvc-0 {
1798 dmas = <&audma1 0xbc>;
1802 dmas = <&audma1 0xbe>;
1808 mix0: mix-0 { };
1813 ctu00: ctu-0 { };
1824 src0: src-0 {
1826 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1831 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1836 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1841 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1846 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1851 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1856 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1861 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1866 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1871 dmas = <&audma0 0x97>, <&audma1 0xba>;
1877 ssiu00: ssiu-0 {
1878 dmas = <&audma0 0x15>, <&audma1 0x16>;
1882 dmas = <&audma0 0x35>, <&audma1 0x36>;
1886 dmas = <&audma0 0x37>, <&audma1 0x38>;
1890 dmas = <&audma0 0x47>, <&audma1 0x48>;
1894 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1898 dmas = <&audma0 0x43>, <&audma1 0x44>;
1902 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1906 dmas = <&audma0 0x53>, <&audma1 0x54>;
1910 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1914 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1918 dmas = <&audma0 0x57>, <&audma1 0x58>;
1922 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1926 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1930 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1934 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1938 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1942 dmas = <&audma0 0x63>, <&audma1 0x64>;
1946 dmas = <&audma0 0x67>, <&audma1 0x68>;
1950 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1954 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1958 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1962 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1966 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1970 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1974 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1978 dmas = <&audma0 0x21>, <&audma1 0x22>;
1982 dmas = <&audma0 0x23>, <&audma1 0x24>;
1986 dmas = <&audma0 0x25>, <&audma1 0x26>;
1990 dmas = <&audma0 0x27>, <&audma1 0x28>;
1994 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1998 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2002 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2006 dmas = <&audma0 0x71>, <&audma1 0x72>;
2010 dmas = <&audma0 0x17>, <&audma1 0x18>;
2014 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2018 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2022 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2026 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2030 dmas = <&audma0 0x31>, <&audma1 0x32>;
2034 dmas = <&audma0 0x33>, <&audma1 0x34>;
2038 dmas = <&audma0 0x73>, <&audma1 0x74>;
2042 dmas = <&audma0 0x75>, <&audma1 0x76>;
2046 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2050 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2054 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2058 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2062 dmas = <&audma0 0x81>, <&audma1 0x82>;
2066 dmas = <&audma0 0x83>, <&audma1 0x84>;
2070 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2074 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2078 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2082 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2088 ssi0: ssi-0 {
2090 dmas = <&audma0 0x01>, <&audma1 0x02>;
2095 dmas = <&audma0 0x03>, <&audma1 0x04>;
2100 dmas = <&audma0 0x05>, <&audma1 0x06>;
2105 dmas = <&audma0 0x07>, <&audma1 0x08>;
2110 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2115 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2120 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2125 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2130 dmas = <&audma0 0x11>, <&audma1 0x12>;
2135 dmas = <&audma0 0x13>, <&audma1 0x14>;
2144 reg = <0 0xec520000 0 0x800>;
2156 reg = <0 0xec700000 0 0x10000>;
2190 reg = <0 0xec720000 0 0x10000>;
2224 reg = <0 0xee000000 0 0xc00>;
2235 reg = <0 0xee020000 0 0x400>;
2245 reg = <0 0xee080000 0 0x100>;
2257 reg = <0 0xee0a0000 0 0x100>;
2269 reg = <0 0xee080100 0 0x100>;
2282 reg = <0 0xee0a0100 0 0x100>;
2296 reg = <0 0xee080200 0 0x700>;
2308 reg = <0 0xee0a0200 0 0x700>;
2319 reg = <0 0xee100000 0 0x2000>;
2333 reg = <0 0xee120000 0 0x2000>;
2347 reg = <0 0xee140000 0 0x2000>;
2361 reg = <0 0xee160000 0 0x2000>;
2375 reg = <0 0xee200000 0 0x200>,
2376 <0 0x08000000 0 0x04000000>,
2377 <0 0xee208000 0 0x100>;
2384 #size-cells = <0>;
2391 reg = <0 0xee300000 0 0x200000>;
2402 #address-cells = <0>;
2404 reg = <0x0 0xf1010000 0 0x1000>,
2405 <0x0 0xf1020000 0 0x20000>,
2406 <0x0 0xf1040000 0 0x20000>,
2407 <0x0 0xf1060000 0 0x20000>;
2419 reg = <0 0xfe000000 0 0x80000>;
2422 bus-range = <0x00 0xff>;
2424 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2425 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2426 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2427 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2429 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2434 interrupt-map-mask = <0 0 0 0>;
2435 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2446 reg = <0 0xee800000 0 0x80000>;
2449 bus-range = <0x00 0xff>;
2451 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2452 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2453 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2454 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2456 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2461 interrupt-map-mask = <0 0 0 0>;
2462 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2472 reg = <0 0xfe940000 0 0x2400>;
2482 reg = <0 0xfe950000 0 0x200>;
2490 reg = <0 0xfe960000 0 0x8000>;
2501 reg = <0 0xfe9a0000 0 0x8000>;
2512 reg = <0 0xfea20000 0 0x5000>;
2523 reg = <0 0xfea28000 0 0x5000>;
2534 reg = <0 0xfe96f000 0 0x200>;
2542 reg = <0 0xfea27000 0 0x200>;
2550 reg = <0 0xfea2f000 0 0x200>;
2558 reg = <0 0xfe9af000 0 0x200>;
2567 reg = <0 0xfea40000 0 0x1000>;
2576 reg = <0 0xfea50000 0 0x1000>;
2585 reg = <0 0xfea70000 0 0x1000>;
2593 reg = <0 0xfea80000 0 0x10000>;
2602 #size-cells = <0>;
2604 port@0 {
2605 reg = <0>;
2610 #size-cells = <0>;
2614 csi20vin0: endpoint@0 {
2615 reg = <0>;
2652 reg = <0 0xfeaa0000 0 0x10000>;
2661 #size-cells = <0>;
2663 port@0 {
2664 reg = <0>;
2669 #size-cells = <0>;
2673 csi40vin0: endpoint@0 {
2674 reg = <0>;
2712 reg = <0 0xfead0000 0 0x10000>;
2723 #size-cells = <0>;
2724 port@0 {
2725 reg = <0>;
2738 reg = <0 0xfeb00000 0 0x80000>;
2744 clock-names = "du.0", "du.1", "du.3";
2746 reset-names = "du.0", "du.3";
2749 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2755 #size-cells = <0>;
2757 port@0 {
2758 reg = <0>;
2777 reg = <0 0xfeb90000 0 0x14>;
2785 #size-cells = <0>;
2787 port@0 {
2788 reg = <0>;
2801 reg = <0 0xfff00044 0 4>;
2809 thermal-sensors = <&tsc 0>;
2878 #clock-cells = <0>;
2879 clock-frequency = <0>;
2884 #clock-cells = <0>;
2885 clock-frequency = <0>;