Lines Matching +full:0 +full:xee000000
20 * The external audio clocks are configured as 0 Hz fixed frequency
26 #clock-cells = <0>;
27 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
49 cluster0_opp: opp-table-0 {
118 #size-cells = <0>;
146 a57_0: cpu@0 {
148 reg = <0x0>;
163 reg = <0x1>;
177 reg = <0x100>;
192 reg = <0x101>;
205 reg = <0x102>;
218 reg = <0x103>;
229 L2_CA57: cache-controller-0 {
246 CPU_SLEEP_0: cpu-sleep-0 {
248 arm,psci-suspend-param = <0x0010000>;
257 arm,psci-suspend-param = <0x0010000>;
268 #clock-cells = <0>;
270 clock-frequency = <0>;
275 #clock-cells = <0>;
277 clock-frequency = <0>;
283 #clock-cells = <0>;
284 clock-frequency = <0>;
311 #clock-cells = <0>;
312 clock-frequency = <0>;
325 reg = <0 0xe6020000 0 0x0c>;
336 reg = <0 0xe6050000 0 0x50>;
340 gpio-ranges = <&pfc 0 0 16>;
351 reg = <0 0xe6051000 0 0x50>;
355 gpio-ranges = <&pfc 0 32 29>;
366 reg = <0 0xe6052000 0 0x50>;
370 gpio-ranges = <&pfc 0 64 15>;
381 reg = <0 0xe6053000 0 0x50>;
385 gpio-ranges = <&pfc 0 96 16>;
396 reg = <0 0xe6054000 0 0x50>;
400 gpio-ranges = <&pfc 0 128 18>;
411 reg = <0 0xe6055000 0 0x50>;
415 gpio-ranges = <&pfc 0 160 26>;
426 reg = <0 0xe6055400 0 0x50>;
430 gpio-ranges = <&pfc 0 192 32>;
441 reg = <0 0xe6055800 0 0x50>;
445 gpio-ranges = <&pfc 0 224 4>;
455 reg = <0 0xe6060000 0 0x50c>;
461 reg = <0 0xe60f0000 0 0x1004>;
474 reg = <0 0xe6130000 0 0x1004>;
493 reg = <0 0xe6140000 0 0x1004>;
512 reg = <0 0xe6148000 0 0x1004>;
530 reg = <0 0xe6150000 0 0x1000>;
534 #power-domain-cells = <0>;
540 reg = <0 0xe6160000 0 0x0200>;
545 reg = <0 0xe6180000 0 0x0400>;
551 reg = <0 0xe6198000 0 0x100>,
552 <0 0xe61a0000 0 0x100>,
553 <0 0xe61a8000 0 0x100>;
567 reg = <0 0xe61c0000 0 0x200>;
568 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
581 reg = <0 0xe61e0000 0 0x30>;
594 reg = <0 0xe6fc0000 0 0x30>;
607 reg = <0 0xe6fd0000 0 0x30>;
620 reg = <0 0xe6fe0000 0 0x30>;
633 reg = <0 0xffc00000 0 0x30>;
646 #size-cells = <0>;
649 reg = <0 0xe6500000 0 0x40>;
654 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
655 <&dmac2 0x91>, <&dmac2 0x90>;
663 #size-cells = <0>;
666 reg = <0 0xe6508000 0 0x40>;
671 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
672 <&dmac2 0x93>, <&dmac2 0x92>;
680 #size-cells = <0>;
683 reg = <0 0xe6510000 0 0x40>;
688 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
689 <&dmac2 0x95>, <&dmac2 0x94>;
697 #size-cells = <0>;
700 reg = <0 0xe66d0000 0 0x40>;
705 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
713 #size-cells = <0>;
716 reg = <0 0xe66d8000 0 0x40>;
721 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
729 #size-cells = <0>;
732 reg = <0 0xe66e0000 0 0x40>;
737 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
745 #size-cells = <0>;
748 reg = <0 0xe66e8000 0 0x40>;
753 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
761 #size-cells = <0>;
765 reg = <0 0xe60b0000 0 0x425>;
770 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
779 reg = <0 0xe6540000 0 0x60>;
785 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
786 <&dmac2 0x31>, <&dmac2 0x30>;
797 reg = <0 0xe6550000 0 0x60>;
803 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
804 <&dmac2 0x33>, <&dmac2 0x32>;
815 reg = <0 0xe6560000 0 0x60>;
821 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
822 <&dmac2 0x35>, <&dmac2 0x34>;
833 reg = <0 0xe66a0000 0 0x60>;
839 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
850 reg = <0 0xe66b0000 0 0x60>;
856 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
866 reg = <0 0xe6590000 0 0x200>;
869 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
870 <&usb_dmac1 0>, <&usb_dmac1 1>;
883 reg = <0 0xe65a0000 0 0x100>;
897 reg = <0 0xe65b0000 0 0x100>;
911 reg = <0 0xe65ee000 0 0x90>;
917 #phy-cells = <0>;
924 reg = <0x0 0xe6601000 0 0x1000>;
933 reg = <0 0xe6700000 0 0x10000>;
962 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
975 reg = <0 0xe7300000 0 0x10000>;
1004 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1017 reg = <0 0xe7310000 0 0x10000>;
1058 reg = <0 0xe6740000 0 0x1000>;
1059 renesas,ipmmu-main = <&ipmmu_mm 0>;
1066 reg = <0 0xe7740000 0 0x1000>;
1074 reg = <0 0xe6570000 0 0x1000>;
1082 reg = <0 0xff8b0000 0 0x1000>;
1090 reg = <0 0xe67b0000 0 0x1000>;
1099 reg = <0 0xec670000 0 0x1000>;
1107 reg = <0 0xfd800000 0 0x1000>;
1115 reg = <0 0xfd950000 0 0x1000>;
1123 reg = <0 0xffc80000 0 0x1000>;
1131 reg = <0 0xfe6b0000 0 0x1000>;
1139 reg = <0 0xfebd0000 0 0x1000>;
1148 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1186 rx-internal-delay-ps = <0>;
1187 tx-internal-delay-ps = <0>;
1190 #size-cells = <0>;
1197 reg = <0 0xe6c30000 0 0x1000>;
1213 reg = <0 0xe6c38000 0 0x1000>;
1229 reg = <0 0xe66c0000 0 0x8000>;
1254 reg = <0 0xe6e30000 0 8>;
1264 reg = <0 0xe6e31000 0 8>;
1274 reg = <0 0xe6e32000 0 8>;
1284 reg = <0 0xe6e33000 0 8>;
1294 reg = <0 0xe6e34000 0 8>;
1304 reg = <0 0xe6e35000 0 8>;
1314 reg = <0 0xe6e36000 0 8>;
1325 reg = <0 0xe6e60000 0 64>;
1331 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1332 <&dmac2 0x51>, <&dmac2 0x50>;
1342 reg = <0 0xe6e68000 0 64>;
1348 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1349 <&dmac2 0x53>, <&dmac2 0x52>;
1359 reg = <0 0xe6e88000 0 64>;
1365 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1366 <&dmac2 0x13>, <&dmac2 0x12>;
1376 reg = <0 0xe6c50000 0 64>;
1382 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1392 reg = <0 0xe6c40000 0 64>;
1398 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1408 reg = <0 0xe6f30000 0 64>;
1414 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1415 <&dmac2 0x5b>, <&dmac2 0x5a>;
1424 reg = <0 0xe6e80000 0 0x148>;
1436 reg = <0 0xe6e90000 0 0x0064>;
1439 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1440 <&dmac2 0x41>, <&dmac2 0x40>;
1445 #size-cells = <0>;
1452 reg = <0 0xe6ea0000 0 0x0064>;
1455 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1456 <&dmac2 0x43>, <&dmac2 0x42>;
1461 #size-cells = <0>;
1468 reg = <0 0xe6c00000 0 0x0064>;
1471 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1476 #size-cells = <0>;
1483 reg = <0 0xe6c10000 0 0x0064>;
1486 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1491 #size-cells = <0>;
1497 reg = <0 0xe6ef0000 0 0x1000>;
1502 renesas,id = <0>;
1507 #size-cells = <0>;
1511 #size-cells = <0>;
1515 vin0csi20: endpoint@0 {
1516 reg = <0>;
1529 reg = <0 0xe6ef1000 0 0x1000>;
1539 #size-cells = <0>;
1543 #size-cells = <0>;
1547 vin1csi20: endpoint@0 {
1548 reg = <0>;
1561 reg = <0 0xe6ef2000 0 0x1000>;
1571 #size-cells = <0>;
1575 #size-cells = <0>;
1579 vin2csi20: endpoint@0 {
1580 reg = <0>;
1593 reg = <0 0xe6ef3000 0 0x1000>;
1603 #size-cells = <0>;
1607 #size-cells = <0>;
1611 vin3csi20: endpoint@0 {
1612 reg = <0>;
1625 reg = <0 0xe6ef4000 0 0x1000>;
1635 #size-cells = <0>;
1639 #size-cells = <0>;
1643 vin4csi20: endpoint@0 {
1644 reg = <0>;
1657 reg = <0 0xe6ef5000 0 0x1000>;
1667 #size-cells = <0>;
1671 #size-cells = <0>;
1675 vin5csi20: endpoint@0 {
1676 reg = <0>;
1689 reg = <0 0xe6ef6000 0 0x1000>;
1699 #size-cells = <0>;
1703 #size-cells = <0>;
1707 vin6csi20: endpoint@0 {
1708 reg = <0>;
1721 reg = <0 0xe6ef7000 0 0x1000>;
1731 #size-cells = <0>;
1735 #size-cells = <0>;
1739 vin7csi20: endpoint@0 {
1740 reg = <0>;
1754 reg = <0 0xe6f40000 0 0x64>;
1758 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1769 reg = <0 0xe6f50000 0 0x64>;
1773 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1784 reg = <0 0xe6f60000 0 0x64>;
1788 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1799 reg = <0 0xe6f70000 0 0x64>;
1803 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1814 reg = <0 0xe6f80000 0 0x64>;
1818 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1829 reg = <0 0xe6f90000 0 0x64>;
1833 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1844 reg = <0 0xe6fa0000 0 0x64>;
1848 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1859 reg = <0 0xe6fb0000 0 0x64>;
1863 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1875 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1881 * clkout : #clock-cells = <0>; <&rcar_sound>;
1885 reg = <0 0xec500000 0 0x1000>, /* SCU */
1886 <0 0xec5a0000 0 0x100>, /* ADG */
1887 <0 0xec540000 0 0x1000>, /* SSIU */
1888 <0 0xec541000 0 0x280>, /* SSI */
1889 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1912 "ssi.1", "ssi.0",
1915 "src.1", "src.0",
1916 "mix.1", "mix.0",
1917 "ctu.1", "ctu.0",
1918 "dvc.0", "dvc.1",
1930 "ssi.1", "ssi.0";
1934 ctu00: ctu-0 { };
1945 dvc0: dvc-0 {
1946 dmas = <&audma1 0xbc>;
1950 dmas = <&audma1 0xbe>;
1956 mix0: mix-0 { };
1961 src0: src-0 {
1963 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1968 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1973 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1978 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1983 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1988 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1993 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1998 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2003 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2008 dmas = <&audma0 0x97>, <&audma1 0xba>;
2014 ssi0: ssi-0 {
2016 dmas = <&audma0 0x01>, <&audma1 0x02>;
2021 dmas = <&audma0 0x03>, <&audma1 0x04>;
2026 dmas = <&audma0 0x05>, <&audma1 0x06>;
2031 dmas = <&audma0 0x07>, <&audma1 0x08>;
2036 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2041 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2046 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2051 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2056 dmas = <&audma0 0x11>, <&audma1 0x12>;
2061 dmas = <&audma0 0x13>, <&audma1 0x14>;
2067 ssiu00: ssiu-0 {
2068 dmas = <&audma0 0x15>, <&audma1 0x16>;
2072 dmas = <&audma0 0x35>, <&audma1 0x36>;
2076 dmas = <&audma0 0x37>, <&audma1 0x38>;
2080 dmas = <&audma0 0x47>, <&audma1 0x48>;
2084 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2088 dmas = <&audma0 0x43>, <&audma1 0x44>;
2092 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2096 dmas = <&audma0 0x53>, <&audma1 0x54>;
2100 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2104 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2108 dmas = <&audma0 0x57>, <&audma1 0x58>;
2112 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2116 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2120 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2124 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2128 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2132 dmas = <&audma0 0x63>, <&audma1 0x64>;
2136 dmas = <&audma0 0x67>, <&audma1 0x68>;
2140 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2144 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2148 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2152 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2156 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2160 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2164 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2168 dmas = <&audma0 0x21>, <&audma1 0x22>;
2172 dmas = <&audma0 0x23>, <&audma1 0x24>;
2176 dmas = <&audma0 0x25>, <&audma1 0x26>;
2180 dmas = <&audma0 0x27>, <&audma1 0x28>;
2184 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2188 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2192 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2196 dmas = <&audma0 0x71>, <&audma1 0x72>;
2200 dmas = <&audma0 0x17>, <&audma1 0x18>;
2204 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2208 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2212 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2216 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2220 dmas = <&audma0 0x31>, <&audma1 0x32>;
2224 dmas = <&audma0 0x33>, <&audma1 0x34>;
2228 dmas = <&audma0 0x73>, <&audma1 0x74>;
2232 dmas = <&audma0 0x75>, <&audma1 0x76>;
2236 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2240 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2244 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2248 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2252 dmas = <&audma0 0x81>, <&audma1 0x82>;
2256 dmas = <&audma0 0x83>, <&audma1 0x84>;
2260 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2264 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2268 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2272 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2281 reg = <0 0xec520000 0 0x800>;
2293 reg = <0 0xec700000 0 0x10000>;
2322 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2335 reg = <0 0xec720000 0 0x10000>;
2377 reg = <0 0xee000000 0 0xc00>;
2388 reg = <0 0xee020000 0 0x400>;
2398 reg = <0 0xee080000 0 0x100>;
2410 reg = <0 0xee0a0000 0 0x100>;
2422 reg = <0 0xee080100 0 0x100>;
2435 reg = <0 0xee0a0100 0 0x100>;
2449 reg = <0 0xee080200 0 0x700>;
2461 reg = <0 0xee0a0200 0 0x700>;
2472 reg = <0 0xee100000 0 0x2000>;
2486 reg = <0 0xee120000 0 0x2000>;
2500 reg = <0 0xee140000 0 0x2000>;
2514 reg = <0 0xee160000 0 0x2000>;
2528 reg = <0 0xee200000 0 0x200>,
2529 <0 0x08000000 0 0x04000000>,
2530 <0 0xee208000 0 0x100>;
2537 #size-cells = <0>;
2544 #address-cells = <0>;
2546 reg = <0x0 0xf1010000 0 0x1000>,
2547 <0x0 0xf1020000 0 0x20000>,
2548 <0x0 0xf1040000 0 0x20000>,
2549 <0x0 0xf1060000 0 0x20000>;
2561 reg = <0 0xfe000000 0 0x80000>;
2564 bus-range = <0x00 0xff>;
2566 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2567 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2568 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2569 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2571 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2576 interrupt-map-mask = <0 0 0 0>;
2577 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2588 reg = <0 0xee800000 0 0x80000>;
2591 bus-range = <0x00 0xff>;
2593 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2594 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2595 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2596 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2598 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2603 interrupt-map-mask = <0 0 0 0>;
2604 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2615 reg = <0 0xfe860000 0 0x2000>;
2625 reg = <0 0xfe870000 0 0x2000>;
2634 reg = <0 0xfe940000 0 0x2400>;
2644 reg = <0 0xfe950000 0 0x200>;
2652 reg = <0 0xfe96f000 0 0x200>;
2660 reg = <0 0xfe9af000 0 0x200>;
2669 reg = <0 0xfea27000 0 0x200>;
2678 reg = <0 0xfea2f000 0 0x200>;
2687 reg = <0 0xfea37000 0 0x200>;
2696 reg = <0 0xfe960000 0 0x8000>;
2707 reg = <0 0xfea20000 0 0x5000>;
2718 reg = <0 0xfea28000 0 0x5000>;
2729 reg = <0 0xfea30000 0 0x5000>;
2740 reg = <0 0xfe9a0000 0 0x8000>;
2752 reg = <0 0xfea40000 0 0x1000>;
2761 reg = <0 0xfea50000 0 0x1000>;
2770 reg = <0 0xfea60000 0 0x1000>;
2778 reg = <0 0xfea80000 0 0x10000>;
2787 #size-cells = <0>;
2789 port@0 {
2790 reg = <0>;
2795 #size-cells = <0>;
2799 csi20vin0: endpoint@0 {
2800 reg = <0>;
2837 reg = <0 0xfeaa0000 0 0x10000>;
2846 #size-cells = <0>;
2848 port@0 {
2849 reg = <0>;
2854 #size-cells = <0>;
2858 csi40vin0: endpoint@0 {
2859 reg = <0>;
2897 reg = <0 0xfead0000 0 0x10000>;
2907 #size-cells = <0>;
2908 port@0 {
2909 reg = <0>;
2926 reg = <0 0xfeb00000 0 0x70000>;
2932 clock-names = "du.0", "du.1", "du.2";
2934 reset-names = "du.0", "du.2";
2937 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2943 #size-cells = <0>;
2945 port@0 {
2946 reg = <0>;
2965 reg = <0 0xfeb90000 0 0x14>;
2973 #size-cells = <0>;
2975 port@0 {
2976 reg = <0>;
2989 reg = <0 0xfff00044 0 4>;
2997 thermal-sensors = <&tsc 0>;
3038 cooling-device = <&a53_0 0 2>;
3069 #clock-cells = <0>;
3070 clock-frequency = <0>;
3075 #clock-cells = <0>;
3076 clock-frequency = <0>;