Lines Matching +full:0 +full:xe66d8000
25 * The external audio clocks are configured as 0 Hz fixed frequency
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
54 cluster0_opp: opp-table-0 {
111 #size-cells = <0>;
145 a57_0: cpu@0 {
147 reg = <0x0>;
162 reg = <0x1>;
176 reg = <0x2>;
190 reg = <0x3>;
204 reg = <0x100>;
219 reg = <0x101>;
232 reg = <0x102>;
245 reg = <0x103>;
256 L2_CA57: cache-controller-0 {
273 CPU_SLEEP_0: cpu-sleep-0 {
275 arm,psci-suspend-param = <0x0010000>;
284 arm,psci-suspend-param = <0x0010000>;
295 #clock-cells = <0>;
297 clock-frequency = <0>;
302 #clock-cells = <0>;
304 clock-frequency = <0>;
310 #clock-cells = <0>;
311 clock-frequency = <0>;
346 #clock-cells = <0>;
347 clock-frequency = <0>;
360 reg = <0 0xe6020000 0 0x0c>;
371 reg = <0 0xe6050000 0 0x50>;
375 gpio-ranges = <&pfc 0 0 16>;
386 reg = <0 0xe6051000 0 0x50>;
390 gpio-ranges = <&pfc 0 32 29>;
401 reg = <0 0xe6052000 0 0x50>;
405 gpio-ranges = <&pfc 0 64 15>;
416 reg = <0 0xe6053000 0 0x50>;
420 gpio-ranges = <&pfc 0 96 16>;
431 reg = <0 0xe6054000 0 0x50>;
435 gpio-ranges = <&pfc 0 128 18>;
446 reg = <0 0xe6055000 0 0x50>;
450 gpio-ranges = <&pfc 0 160 26>;
461 reg = <0 0xe6055400 0 0x50>;
465 gpio-ranges = <&pfc 0 192 32>;
476 reg = <0 0xe6055800 0 0x50>;
480 gpio-ranges = <&pfc 0 224 4>;
490 reg = <0 0xe6060000 0 0x50c>;
496 reg = <0 0xe60f0000 0 0x1004>;
509 reg = <0 0xe6130000 0 0x1004>;
528 reg = <0 0xe6140000 0 0x1004>;
547 reg = <0 0xe6148000 0 0x1004>;
565 reg = <0 0xe6150000 0 0x1000>;
569 #power-domain-cells = <0>;
575 reg = <0 0xe6160000 0 0x0200>;
580 reg = <0 0xe6180000 0 0x0400>;
586 reg = <0 0xe6198000 0 0x100>,
587 <0 0xe61a0000 0 0x100>,
588 <0 0xe61a8000 0 0x100>;
602 reg = <0 0xe61c0000 0 0x200>;
603 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
616 reg = <0 0xe61e0000 0 0x30>;
629 reg = <0 0xe6fc0000 0 0x30>;
642 reg = <0 0xe6fd0000 0 0x30>;
655 reg = <0 0xe6fe0000 0 0x30>;
668 reg = <0 0xffc00000 0 0x30>;
681 #size-cells = <0>;
684 reg = <0 0xe6500000 0 0x40>;
689 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
690 <&dmac2 0x91>, <&dmac2 0x90>;
698 #size-cells = <0>;
701 reg = <0 0xe6508000 0 0x40>;
706 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
707 <&dmac2 0x93>, <&dmac2 0x92>;
715 #size-cells = <0>;
718 reg = <0 0xe6510000 0 0x40>;
723 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
724 <&dmac2 0x95>, <&dmac2 0x94>;
732 #size-cells = <0>;
735 reg = <0 0xe66d0000 0 0x40>;
740 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
748 #size-cells = <0>;
751 reg = <0 0xe66d8000 0 0x40>;
756 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
764 #size-cells = <0>;
767 reg = <0 0xe66e0000 0 0x40>;
772 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
780 #size-cells = <0>;
783 reg = <0 0xe66e8000 0 0x40>;
788 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
796 #size-cells = <0>;
800 reg = <0 0xe60b0000 0 0x425>;
805 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
814 reg = <0 0xe6540000 0 96>;
820 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
821 <&dmac2 0x31>, <&dmac2 0x30>;
832 reg = <0 0xe6550000 0 96>;
838 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
839 <&dmac2 0x33>, <&dmac2 0x32>;
850 reg = <0 0xe6560000 0 96>;
856 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
857 <&dmac2 0x35>, <&dmac2 0x34>;
868 reg = <0 0xe66a0000 0 96>;
874 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
885 reg = <0 0xe66b0000 0 96>;
891 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
901 reg = <0 0xe6590000 0 0x200>;
904 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
905 <&usb_dmac1 0>, <&usb_dmac1 1>;
918 reg = <0 0xe659c000 0 0x200>;
921 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
922 <&usb_dmac3 0>, <&usb_dmac3 1>;
935 reg = <0 0xe65a0000 0 0x100>;
949 reg = <0 0xe65b0000 0 0x100>;
963 reg = <0 0xe6460000 0 0x100>;
977 reg = <0 0xe6470000 0 0x100>;
991 reg = <0 0xe65ee000 0 0x90>;
997 #phy-cells = <0>;
1004 reg = <0x0 0xe6601000 0 0x1000>;
1013 reg = <0 0xe6700000 0 0x10000>;
1042 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1055 reg = <0 0xe7300000 0 0x10000>;
1084 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1097 reg = <0 0xe7310000 0 0x10000>;
1138 reg = <0 0xe6740000 0 0x1000>;
1139 renesas,ipmmu-main = <&ipmmu_mm 0>;
1146 reg = <0 0xe7740000 0 0x1000>;
1154 reg = <0 0xe6570000 0 0x1000>;
1162 reg = <0 0xff8b0000 0 0x1000>;
1170 reg = <0 0xe67b0000 0 0x1000>;
1179 reg = <0 0xec670000 0 0x1000>;
1187 reg = <0 0xfd800000 0 0x1000>;
1195 reg = <0 0xfd950000 0 0x1000>;
1203 reg = <0 0xfd960000 0 0x1000>;
1211 reg = <0 0xfd970000 0 0x1000>;
1219 reg = <0 0xffc80000 0 0x1000>;
1227 reg = <0 0xfe6b0000 0 0x1000>;
1235 reg = <0 0xfe6f0000 0 0x1000>;
1243 reg = <0 0xfebd0000 0 0x1000>;
1251 reg = <0 0xfebe0000 0 0x1000>;
1259 reg = <0 0xfe990000 0 0x1000>;
1267 reg = <0 0xfe980000 0 0x1000>;
1276 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1314 rx-internal-delay-ps = <0>;
1315 tx-internal-delay-ps = <0>;
1318 #size-cells = <0>;
1325 reg = <0 0xe6c30000 0 0x1000>;
1341 reg = <0 0xe6c38000 0 0x1000>;
1357 reg = <0 0xe66c0000 0 0x8000>;
1382 reg = <0 0xe6e30000 0 0x8>;
1392 reg = <0 0xe6e31000 0 0x8>;
1402 reg = <0 0xe6e32000 0 0x8>;
1412 reg = <0 0xe6e33000 0 0x8>;
1422 reg = <0 0xe6e34000 0 0x8>;
1432 reg = <0 0xe6e35000 0 0x8>;
1442 reg = <0 0xe6e36000 0 0x8>;
1453 reg = <0 0xe6e60000 0 64>;
1459 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1460 <&dmac2 0x51>, <&dmac2 0x50>;
1470 reg = <0 0xe6e68000 0 64>;
1476 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1477 <&dmac2 0x53>, <&dmac2 0x52>;
1487 reg = <0 0xe6e88000 0 64>;
1493 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1494 <&dmac2 0x13>, <&dmac2 0x12>;
1504 reg = <0 0xe6c50000 0 64>;
1510 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1520 reg = <0 0xe6c40000 0 64>;
1526 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1536 reg = <0 0xe6f30000 0 64>;
1542 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1543 <&dmac2 0x5b>, <&dmac2 0x5a>;
1552 reg = <0 0xe6e80000 0 0x148>;
1564 reg = <0 0xe6e90000 0 0x0064>;
1567 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1568 <&dmac2 0x41>, <&dmac2 0x40>;
1573 #size-cells = <0>;
1580 reg = <0 0xe6ea0000 0 0x0064>;
1583 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1584 <&dmac2 0x43>, <&dmac2 0x42>;
1589 #size-cells = <0>;
1596 reg = <0 0xe6c00000 0 0x0064>;
1599 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1604 #size-cells = <0>;
1611 reg = <0 0xe6c10000 0 0x0064>;
1614 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1619 #size-cells = <0>;
1625 reg = <0 0xe6ef0000 0 0x1000>;
1630 renesas,id = <0>;
1635 #size-cells = <0>;
1639 #size-cells = <0>;
1643 vin0csi20: endpoint@0 {
1644 reg = <0>;
1657 reg = <0 0xe6ef1000 0 0x1000>;
1667 #size-cells = <0>;
1671 #size-cells = <0>;
1675 vin1csi20: endpoint@0 {
1676 reg = <0>;
1689 reg = <0 0xe6ef2000 0 0x1000>;
1699 #size-cells = <0>;
1703 #size-cells = <0>;
1707 vin2csi20: endpoint@0 {
1708 reg = <0>;
1721 reg = <0 0xe6ef3000 0 0x1000>;
1731 #size-cells = <0>;
1735 #size-cells = <0>;
1739 vin3csi20: endpoint@0 {
1740 reg = <0>;
1753 reg = <0 0xe6ef4000 0 0x1000>;
1763 #size-cells = <0>;
1767 #size-cells = <0>;
1771 vin4csi20: endpoint@0 {
1772 reg = <0>;
1785 reg = <0 0xe6ef5000 0 0x1000>;
1795 #size-cells = <0>;
1799 #size-cells = <0>;
1803 vin5csi20: endpoint@0 {
1804 reg = <0>;
1817 reg = <0 0xe6ef6000 0 0x1000>;
1827 #size-cells = <0>;
1831 #size-cells = <0>;
1835 vin6csi20: endpoint@0 {
1836 reg = <0>;
1849 reg = <0 0xe6ef7000 0 0x1000>;
1859 #size-cells = <0>;
1863 #size-cells = <0>;
1867 vin7csi20: endpoint@0 {
1868 reg = <0>;
1882 reg = <0 0xe6f40000 0 0x64>;
1886 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1897 reg = <0 0xe6f50000 0 0x64>;
1901 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1912 reg = <0 0xe6f60000 0 0x64>;
1916 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1927 reg = <0 0xe6f70000 0 0x64>;
1931 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1942 reg = <0 0xe6f80000 0 0x64>;
1946 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1957 reg = <0 0xe6f90000 0 0x64>;
1961 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1972 reg = <0 0xe6fa0000 0 0x64>;
1976 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1987 reg = <0 0xe6fb0000 0 0x64>;
1991 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
2003 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
2009 * clkout : #clock-cells = <0>; <&rcar_sound>;
2013 reg = <0 0xec500000 0 0x1000>, /* SCU */
2014 <0 0xec5a0000 0 0x100>, /* ADG */
2015 <0 0xec540000 0 0x1000>, /* SSIU */
2016 <0 0xec541000 0 0x280>, /* SSI */
2017 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
2040 "ssi.1", "ssi.0",
2043 "src.1", "src.0",
2044 "mix.1", "mix.0",
2045 "ctu.1", "ctu.0",
2046 "dvc.0", "dvc.1",
2058 "ssi.1", "ssi.0";
2062 dvc0: dvc-0 {
2063 dmas = <&audma1 0xbc>;
2067 dmas = <&audma1 0xbe>;
2073 mix0: mix-0 { };
2078 ctu00: ctu-0 { };
2089 src0: src-0 {
2091 dmas = <&audma0 0x85>, <&audma1 0x9a>;
2096 dmas = <&audma0 0x87>, <&audma1 0x9c>;
2101 dmas = <&audma0 0x89>, <&audma1 0x9e>;
2106 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
2111 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
2116 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
2121 dmas = <&audma0 0x91>, <&audma1 0xb4>;
2126 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2131 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2136 dmas = <&audma0 0x97>, <&audma1 0xba>;
2142 ssiu00: ssiu-0 {
2143 dmas = <&audma0 0x15>, <&audma1 0x16>;
2147 dmas = <&audma0 0x35>, <&audma1 0x36>;
2151 dmas = <&audma0 0x37>, <&audma1 0x38>;
2155 dmas = <&audma0 0x47>, <&audma1 0x48>;
2159 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2163 dmas = <&audma0 0x43>, <&audma1 0x44>;
2167 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2171 dmas = <&audma0 0x53>, <&audma1 0x54>;
2175 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2179 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2183 dmas = <&audma0 0x57>, <&audma1 0x58>;
2187 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2191 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2195 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2199 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2203 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2207 dmas = <&audma0 0x63>, <&audma1 0x64>;
2211 dmas = <&audma0 0x67>, <&audma1 0x68>;
2215 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2219 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2223 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2227 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2231 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2235 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2239 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2243 dmas = <&audma0 0x21>, <&audma1 0x22>;
2247 dmas = <&audma0 0x23>, <&audma1 0x24>;
2251 dmas = <&audma0 0x25>, <&audma1 0x26>;
2255 dmas = <&audma0 0x27>, <&audma1 0x28>;
2259 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2263 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2267 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2271 dmas = <&audma0 0x71>, <&audma1 0x72>;
2275 dmas = <&audma0 0x17>, <&audma1 0x18>;
2279 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2283 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2287 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2291 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2295 dmas = <&audma0 0x31>, <&audma1 0x32>;
2299 dmas = <&audma0 0x33>, <&audma1 0x34>;
2303 dmas = <&audma0 0x73>, <&audma1 0x74>;
2307 dmas = <&audma0 0x75>, <&audma1 0x76>;
2311 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2315 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2319 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2323 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2327 dmas = <&audma0 0x81>, <&audma1 0x82>;
2331 dmas = <&audma0 0x83>, <&audma1 0x84>;
2335 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2339 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2343 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2347 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2353 ssi0: ssi-0 {
2355 dmas = <&audma0 0x01>, <&audma1 0x02>;
2360 dmas = <&audma0 0x03>, <&audma1 0x04>;
2365 dmas = <&audma0 0x05>, <&audma1 0x06>;
2370 dmas = <&audma0 0x07>, <&audma1 0x08>;
2375 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2380 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2385 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2390 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2395 dmas = <&audma0 0x11>, <&audma1 0x12>;
2400 dmas = <&audma0 0x13>, <&audma1 0x14>;
2409 reg = <0 0xec520000 0 0x800>;
2421 reg = <0 0xec700000 0 0x10000>;
2450 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2463 reg = <0 0xec720000 0 0x10000>;
2504 reg = <0 0xee000000 0 0xc00>;
2515 reg = <0 0xee020000 0 0x400>;
2525 reg = <0 0xee080000 0 0x100>;
2537 reg = <0 0xee0a0000 0 0x100>;
2549 reg = <0 0xee0c0000 0 0x100>;
2561 reg = <0 0xee0e0000 0 0x100>;
2573 reg = <0 0xee080100 0 0x100>;
2586 reg = <0 0xee0a0100 0 0x100>;
2599 reg = <0 0xee0c0100 0 0x100>;
2612 reg = <0 0xee0e0100 0 0x100>;
2626 reg = <0 0xee080200 0 0x700>;
2638 reg = <0 0xee0a0200 0 0x700>;
2649 reg = <0 0xee0c0200 0 0x700>;
2660 reg = <0 0xee0e0200 0 0x700>;
2672 reg = <0 0xee100000 0 0x2000>;
2686 reg = <0 0xee120000 0 0x2000>;
2700 reg = <0 0xee140000 0 0x2000>;
2714 reg = <0 0xee160000 0 0x2000>;
2728 reg = <0 0xee200000 0 0x200>,
2729 <0 0x08000000 0 0x04000000>,
2730 <0 0xee208000 0 0x100>;
2737 #size-cells = <0>;
2744 reg = <0 0xee300000 0 0x200000>;
2756 #address-cells = <0>;
2758 reg = <0x0 0xf1010000 0 0x1000>,
2759 <0x0 0xf1020000 0 0x20000>,
2760 <0x0 0xf1040000 0 0x20000>,
2761 <0x0 0xf1060000 0 0x20000>;
2773 reg = <0 0xfe000000 0 0x80000>;
2776 bus-range = <0x00 0xff>;
2778 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2779 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2780 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2781 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2783 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2788 interrupt-map-mask = <0 0 0 0>;
2789 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2800 reg = <0 0xee800000 0 0x80000>;
2803 bus-range = <0x00 0xff>;
2805 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2806 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2807 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2808 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2810 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2815 interrupt-map-mask = <0 0 0 0>;
2816 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2827 reg = <0x0 0xfe000000 0 0x80000>,
2828 <0x0 0xfe100000 0 0x100000>,
2829 <0x0 0xfe200000 0 0x200000>,
2830 <0x0 0x30000000 0 0x8000000>,
2831 <0x0 0x38000000 0 0x8000000>;
2846 reg = <0x0 0xee800000 0 0x80000>,
2847 <0x0 0xee900000 0 0x100000>,
2848 <0x0 0xeea00000 0 0x200000>,
2849 <0x0 0xc0000000 0 0x8000000>,
2850 <0x0 0xc8000000 0 0x8000000>;
2865 reg = <0 0xfe860000 0 0x2000>;
2875 reg = <0 0xfe870000 0 0x2000>;
2885 reg = <0 0xfe880000 0 0x2000>;
2895 reg = <0 0xfe890000 0 0x2000>;
2904 reg = <0 0xfe920000 0 0x8000>;
2915 reg = <0 0xfe960000 0 0x8000>;
2926 reg = <0 0xfea20000 0 0x5000>;
2937 reg = <0 0xfea28000 0 0x5000>;
2948 reg = <0 0xfea30000 0 0x5000>;
2959 reg = <0 0xfe9a0000 0 0x8000>;
2970 reg = <0 0xfe9b0000 0 0x8000>;
2981 reg = <0 0xfe940000 0 0x2400>;
2991 reg = <0 0xfe944000 0 0x2400>;
3001 reg = <0 0xfe950000 0 0x200>;
3005 iommus = <&ipmmu_vp0 0>;
3010 reg = <0 0xfe951000 0 0x200>;
3019 reg = <0 0xfe96f000 0 0x200>;
3028 reg = <0 0xfe92f000 0 0x200>;
3037 reg = <0 0xfe9af000 0 0x200>;
3046 reg = <0 0xfe9bf000 0 0x200>;
3055 reg = <0 0xfea27000 0 0x200>;
3064 reg = <0 0xfea2f000 0 0x200>;
3073 reg = <0 0xfea37000 0 0x200>;
3083 reg = <0 0xfea40000 0 0x1000>;
3092 reg = <0 0xfea50000 0 0x1000>;
3101 reg = <0 0xfea60000 0 0x1000>;
3110 reg = <0 0xfea70000 0 0x1000>;
3118 reg = <0 0xfea80000 0 0x10000>;
3127 #size-cells = <0>;
3129 port@0 {
3130 reg = <0>;
3135 #size-cells = <0>;
3139 csi20vin0: endpoint@0 {
3140 reg = <0>;
3177 reg = <0 0xfeaa0000 0 0x10000>;
3186 #size-cells = <0>;
3188 port@0 {
3189 reg = <0>;
3194 #size-cells = <0>;
3198 csi40vin0: endpoint@0 {
3199 reg = <0>;
3220 reg = <0 0xfeab0000 0 0x10000>;
3229 #size-cells = <0>;
3231 port@0 {
3232 reg = <0>;
3237 #size-cells = <0>;
3241 csi41vin4: endpoint@0 {
3242 reg = <0>;
3263 reg = <0 0xfead0000 0 0x10000>;
3273 #size-cells = <0>;
3274 port@0 {
3275 reg = <0>;
3292 reg = <0 0xfeae0000 0 0x10000>;
3302 #size-cells = <0>;
3303 port@0 {
3304 reg = <0>;
3321 reg = <0 0xfeb00000 0 0x80000>;
3328 clock-names = "du.0", "du.1", "du.2", "du.3";
3330 reset-names = "du.0", "du.2";
3333 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>,
3340 #size-cells = <0>;
3342 port@0 {
3343 reg = <0>;
3368 reg = <0 0xfeb90000 0 0x14>;
3376 #size-cells = <0>;
3378 port@0 {
3379 reg = <0>;
3392 reg = <0 0xfff00044 0 4>;
3400 thermal-sensors = <&tsc 0>;
3455 cooling-device = <&a53_0 0 2>;
3473 #clock-cells = <0>;
3474 clock-frequency = <0>;
3479 #clock-cells = <0>;
3480 clock-frequency = <0>;