Lines Matching +full:- +full:resets
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <0>;
40 /* External CAN clock - to be overridden by boards that provide it */
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster1_opp: opp-table-1 {
48 compatible = "operating-points-v2";
49 opp-shared;
50 opp-800000000 {
51 opp-hz = /bits/ 64 <800000000>;
52 opp-microvolt = <820000>;
53 clock-latency-ns = <300000>;
55 opp-1000000000 {
56 opp-hz = /bits/ 64 <1000000000>;
57 opp-microvolt = <820000>;
58 clock-latency-ns = <300000>;
60 opp-1200000000 {
61 opp-hz = /bits/ 64 <1200000000>;
62 opp-microvolt = <820000>;
63 clock-latency-ns = <300000>;
64 opp-suspend;
69 #address-cells = <1>;
70 #size-cells = <0>;
73 compatible = "arm,cortex-a53";
76 #cooling-cells = <2>;
77 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
78 next-level-cache = <&L2_CA53>;
79 enable-method = "psci";
80 dynamic-power-coefficient = <277>;
82 operating-points-v2 = <&cluster1_opp>;
86 compatible = "arm,cortex-a53";
89 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
90 next-level-cache = <&L2_CA53>;
91 enable-method = "psci";
93 operating-points-v2 = <&cluster1_opp>;
96 L2_CA53: cache-controller-0 {
98 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
99 cache-unified;
100 cache-level = <2>;
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
108 clock-frequency = <0>;
111 /* External PCIe clock - can be overridden by the board */
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
119 compatible = "arm,cortex-a53-pmu";
120 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
122 interrupt-affinity = <&a53_0>, <&a53_1>;
126 compatible = "arm,psci-1.0", "arm,psci-0.2";
130 /* External SCIF clock - to be overridden by boards that provide it */
132 compatible = "fixed-clock";
133 #clock-cells = <0>;
134 clock-frequency = <0>;
138 compatible = "simple-bus";
139 interrupt-parent = <&gic>;
140 #address-cells = <2>;
141 #size-cells = <2>;
145 compatible = "renesas,r8a774c0-wdt",
146 "renesas,rcar-gen3-wdt";
150 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
151 resets = <&cpg 402>;
156 compatible = "renesas,gpio-r8a774c0",
157 "renesas,rcar-gen3-gpio";
160 #gpio-cells = <2>;
161 gpio-controller;
162 gpio-ranges = <&pfc 0 0 18>;
163 #interrupt-cells = <2>;
164 interrupt-controller;
166 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
167 resets = <&cpg 912>;
171 compatible = "renesas,gpio-r8a774c0",
172 "renesas,rcar-gen3-gpio";
175 #gpio-cells = <2>;
176 gpio-controller;
177 gpio-ranges = <&pfc 0 32 23>;
178 #interrupt-cells = <2>;
179 interrupt-controller;
181 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
182 resets = <&cpg 911>;
186 compatible = "renesas,gpio-r8a774c0",
187 "renesas,rcar-gen3-gpio";
190 #gpio-cells = <2>;
191 gpio-controller;
192 gpio-ranges = <&pfc 0 64 26>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
196 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
197 resets = <&cpg 910>;
201 compatible = "renesas,gpio-r8a774c0",
202 "renesas,rcar-gen3-gpio";
205 #gpio-cells = <2>;
206 gpio-controller;
207 gpio-ranges = <&pfc 0 96 16>;
208 #interrupt-cells = <2>;
209 interrupt-controller;
211 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
212 resets = <&cpg 909>;
216 compatible = "renesas,gpio-r8a774c0",
217 "renesas,rcar-gen3-gpio";
220 #gpio-cells = <2>;
221 gpio-controller;
222 gpio-ranges = <&pfc 0 128 11>;
223 #interrupt-cells = <2>;
224 interrupt-controller;
226 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
227 resets = <&cpg 908>;
231 compatible = "renesas,gpio-r8a774c0",
232 "renesas,rcar-gen3-gpio";
235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 160 20>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
241 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
242 resets = <&cpg 907>;
246 compatible = "renesas,gpio-r8a774c0",
247 "renesas,rcar-gen3-gpio";
250 #gpio-cells = <2>;
251 gpio-controller;
252 gpio-ranges = <&pfc 0 192 18>;
253 #interrupt-cells = <2>;
254 interrupt-controller;
256 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
257 resets = <&cpg 906>;
261 compatible = "renesas,pfc-r8a774c0";
266 compatible = "renesas,r8a774c0-cmt0",
267 "renesas,rcar-gen3-cmt0";
272 clock-names = "fck";
273 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
274 resets = <&cpg 303>;
279 compatible = "renesas,r8a774c0-cmt1",
280 "renesas,rcar-gen3-cmt1";
291 clock-names = "fck";
292 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
293 resets = <&cpg 302>;
298 compatible = "renesas,r8a774c0-cmt1",
299 "renesas,rcar-gen3-cmt1";
310 clock-names = "fck";
311 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
312 resets = <&cpg 301>;
317 compatible = "renesas,r8a774c0-cmt1",
318 "renesas,rcar-gen3-cmt1";
329 clock-names = "fck";
330 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
331 resets = <&cpg 300>;
335 cpg: clock-controller@e6150000 {
336 compatible = "renesas,r8a774c0-cpg-mssr";
339 clock-names = "extal";
340 #clock-cells = <2>;
341 #power-domain-cells = <0>;
342 #reset-cells = <1>;
345 rst: reset-controller@e6160000 {
346 compatible = "renesas,r8a774c0-rst";
350 sysc: system-controller@e6180000 {
351 compatible = "renesas,r8a774c0-sysc";
353 #power-domain-cells = <1>;
357 compatible = "renesas,thermal-r8a774c0";
363 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
364 resets = <&cpg 522>;
365 #thermal-sensor-cells = <0>;
368 intc_ex: interrupt-controller@e61c0000 {
369 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
370 #interrupt-cells = <2>;
371 interrupt-controller;
380 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
381 resets = <&cpg 407>;
385 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
391 clock-names = "fck";
392 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
393 resets = <&cpg 125>;
398 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
404 clock-names = "fck";
405 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>;
411 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
417 clock-names = "fck";
418 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
419 resets = <&cpg 123>;
424 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
430 clock-names = "fck";
431 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
432 resets = <&cpg 122>;
437 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
443 clock-names = "fck";
444 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
445 resets = <&cpg 121>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "renesas,i2c-r8a774c0",
453 "renesas,rcar-gen3-i2c";
457 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
458 resets = <&cpg 931>;
461 dma-names = "tx", "rx", "tx", "rx";
462 i2c-scl-internal-delay-ns = <110>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "renesas,i2c-r8a774c0",
470 "renesas,rcar-gen3-i2c";
474 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
475 resets = <&cpg 930>;
478 dma-names = "tx", "rx", "tx", "rx";
479 i2c-scl-internal-delay-ns = <6>;
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "renesas,i2c-r8a774c0",
487 "renesas,rcar-gen3-i2c";
491 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
492 resets = <&cpg 929>;
495 dma-names = "tx", "rx", "tx", "rx";
496 i2c-scl-internal-delay-ns = <6>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 compatible = "renesas,i2c-r8a774c0",
504 "renesas,rcar-gen3-i2c";
508 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
509 resets = <&cpg 928>;
511 dma-names = "tx", "rx";
512 i2c-scl-internal-delay-ns = <110>;
517 #address-cells = <1>;
518 #size-cells = <0>;
519 compatible = "renesas,i2c-r8a774c0",
520 "renesas,rcar-gen3-i2c";
524 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
525 resets = <&cpg 927>;
527 dma-names = "tx", "rx";
528 i2c-scl-internal-delay-ns = <6>;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,i2c-r8a774c0",
536 "renesas,rcar-gen3-i2c";
540 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
541 resets = <&cpg 919>;
543 dma-names = "tx", "rx";
544 i2c-scl-internal-delay-ns = <6>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551 compatible = "renesas,i2c-r8a774c0",
552 "renesas,rcar-gen3-i2c";
556 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
557 resets = <&cpg 918>;
559 dma-names = "tx", "rx";
560 i2c-scl-internal-delay-ns = <6>;
565 #address-cells = <1>;
566 #size-cells = <0>;
567 compatible = "renesas,i2c-r8a774c0",
568 "renesas,rcar-gen3-i2c";
572 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
573 resets = <&cpg 1003>;
574 i2c-scl-internal-delay-ns = <6>;
579 #address-cells = <1>;
580 #size-cells = <0>;
581 compatible = "renesas,iic-r8a774c0",
582 "renesas,rcar-gen3-iic",
583 "renesas,rmobile-iic";
587 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
588 resets = <&cpg 926>;
590 dma-names = "tx", "rx";
595 compatible = "renesas,hscif-r8a774c0",
596 "renesas,rcar-gen3-hscif",
603 clock-names = "fck", "brg_int", "scif_clk";
606 dma-names = "tx", "rx", "tx", "rx";
607 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
608 resets = <&cpg 520>;
613 compatible = "renesas,hscif-r8a774c0",
614 "renesas,rcar-gen3-hscif",
621 clock-names = "fck", "brg_int", "scif_clk";
624 dma-names = "tx", "rx", "tx", "rx";
625 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
626 resets = <&cpg 519>;
631 compatible = "renesas,hscif-r8a774c0",
632 "renesas,rcar-gen3-hscif",
639 clock-names = "fck", "brg_int", "scif_clk";
642 dma-names = "tx", "rx", "tx", "rx";
643 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
644 resets = <&cpg 518>;
649 compatible = "renesas,hscif-r8a774c0",
650 "renesas,rcar-gen3-hscif",
657 clock-names = "fck", "brg_int", "scif_clk";
659 dma-names = "tx", "rx";
660 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
661 resets = <&cpg 517>;
666 compatible = "renesas,hscif-r8a774c0",
667 "renesas,rcar-gen3-hscif",
674 clock-names = "fck", "brg_int", "scif_clk";
676 dma-names = "tx", "rx";
677 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
678 resets = <&cpg 516>;
683 compatible = "renesas,usbhs-r8a774c0",
684 "renesas,rcar-gen3-usbhs";
690 dma-names = "ch0", "ch1", "ch2", "ch3";
693 phy-names = "usb";
694 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
695 resets = <&cpg 704>, <&cpg 703>;
699 usb_dmac0: dma-controller@e65a0000 {
700 compatible = "renesas,r8a774c0-usb-dmac",
701 "renesas,usb-dmac";
705 interrupt-names = "ch0", "ch1";
707 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
708 resets = <&cpg 330>;
709 #dma-cells = <1>;
710 dma-channels = <2>;
713 usb_dmac1: dma-controller@e65b0000 {
714 compatible = "renesas,r8a774c0-usb-dmac",
715 "renesas,usb-dmac";
719 interrupt-names = "ch0", "ch1";
721 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
722 resets = <&cpg 331>;
723 #dma-cells = <1>;
724 dma-channels = <2>;
727 dmac0: dma-controller@e6700000 {
728 compatible = "renesas,dmac-r8a774c0",
729 "renesas,rcar-dmac";
748 interrupt-names = "error",
754 clock-names = "fck";
755 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
756 resets = <&cpg 219>;
757 #dma-cells = <1>;
758 dma-channels = <16>;
769 dmac1: dma-controller@e7300000 {
770 compatible = "renesas,dmac-r8a774c0",
771 "renesas,rcar-dmac";
790 interrupt-names = "error",
796 clock-names = "fck";
797 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
798 resets = <&cpg 218>;
799 #dma-cells = <1>;
800 dma-channels = <16>;
811 dmac2: dma-controller@e7310000 {
812 compatible = "renesas,dmac-r8a774c0",
813 "renesas,rcar-dmac";
832 interrupt-names = "error",
838 clock-names = "fck";
839 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
840 resets = <&cpg 217>;
841 #dma-cells = <1>;
842 dma-channels = <16>;
854 compatible = "renesas,ipmmu-r8a774c0";
856 renesas,ipmmu-main = <&ipmmu_mm 0>;
857 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
858 #iommu-cells = <1>;
862 compatible = "renesas,ipmmu-r8a774c0";
864 renesas,ipmmu-main = <&ipmmu_mm 1>;
865 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
866 #iommu-cells = <1>;
870 compatible = "renesas,ipmmu-r8a774c0";
872 renesas,ipmmu-main = <&ipmmu_mm 2>;
873 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
874 #iommu-cells = <1>;
878 compatible = "renesas,ipmmu-r8a774c0";
882 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
883 #iommu-cells = <1>;
887 compatible = "renesas,ipmmu-r8a774c0";
889 renesas,ipmmu-main = <&ipmmu_mm 4>;
890 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
891 #iommu-cells = <1>;
895 compatible = "renesas,ipmmu-r8a774c0";
897 renesas,ipmmu-main = <&ipmmu_mm 6>;
898 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
899 #iommu-cells = <1>;
903 compatible = "renesas,ipmmu-r8a774c0";
905 renesas,ipmmu-main = <&ipmmu_mm 12>;
906 power-domains = <&sysc R8A774C0_PD_A3VC>;
907 #iommu-cells = <1>;
911 compatible = "renesas,ipmmu-r8a774c0";
913 renesas,ipmmu-main = <&ipmmu_mm 14>;
914 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
915 #iommu-cells = <1>;
919 compatible = "renesas,ipmmu-r8a774c0";
921 renesas,ipmmu-main = <&ipmmu_mm 16>;
922 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
923 #iommu-cells = <1>;
927 compatible = "renesas,etheravb-r8a774c0",
928 "renesas,etheravb-rcar-gen3";
955 interrupt-names = "ch0", "ch1", "ch2", "ch3",
963 clock-names = "fck";
964 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
965 resets = <&cpg 812>;
966 phy-mode = "rgmii";
967 rx-internal-delay-ps = <0>;
969 #address-cells = <1>;
970 #size-cells = <0>;
975 compatible = "renesas,can-r8a774c0",
976 "renesas,rcar-gen3-can";
982 clock-names = "clkp1", "clkp2", "can_clk";
983 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
984 assigned-clock-rates = <40000000>;
985 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
986 resets = <&cpg 916>;
991 compatible = "renesas,can-r8a774c0",
992 "renesas,rcar-gen3-can";
998 clock-names = "clkp1", "clkp2", "can_clk";
999 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1000 assigned-clock-rates = <40000000>;
1001 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1002 resets = <&cpg 915>;
1007 compatible = "renesas,r8a774c0-canfd",
1008 "renesas,rcar-gen3-canfd";
1012 interrupt-names = "ch_int", "g_int";
1016 clock-names = "fck", "canfd", "can_clk";
1017 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1018 assigned-clock-rates = <40000000>;
1019 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1020 resets = <&cpg 914>;
1033 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1036 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1037 resets = <&cpg 523>;
1038 #pwm-cells = <2>;
1043 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1046 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1047 resets = <&cpg 523>;
1048 #pwm-cells = <2>;
1053 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1056 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1057 resets = <&cpg 523>;
1058 #pwm-cells = <2>;
1063 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1066 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1067 resets = <&cpg 523>;
1068 #pwm-cells = <2>;
1073 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1076 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1077 resets = <&cpg 523>;
1078 #pwm-cells = <2>;
1083 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1086 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1087 resets = <&cpg 523>;
1088 #pwm-cells = <2>;
1093 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1096 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1097 resets = <&cpg 523>;
1098 #pwm-cells = <2>;
1103 compatible = "renesas,scif-r8a774c0",
1104 "renesas,rcar-gen3-scif", "renesas,scif";
1110 clock-names = "fck", "brg_int", "scif_clk";
1113 dma-names = "tx", "rx", "tx", "rx";
1114 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1115 resets = <&cpg 207>;
1120 compatible = "renesas,scif-r8a774c0",
1121 "renesas,rcar-gen3-scif", "renesas,scif";
1127 clock-names = "fck", "brg_int", "scif_clk";
1130 dma-names = "tx", "rx", "tx", "rx";
1131 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1132 resets = <&cpg 206>;
1137 compatible = "renesas,scif-r8a774c0",
1138 "renesas,rcar-gen3-scif", "renesas,scif";
1144 clock-names = "fck", "brg_int", "scif_clk";
1147 dma-names = "tx", "rx", "tx", "rx";
1148 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1149 resets = <&cpg 310>;
1154 compatible = "renesas,scif-r8a774c0",
1155 "renesas,rcar-gen3-scif", "renesas,scif";
1161 clock-names = "fck", "brg_int", "scif_clk";
1163 dma-names = "tx", "rx";
1164 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1165 resets = <&cpg 204>;
1170 compatible = "renesas,scif-r8a774c0",
1171 "renesas,rcar-gen3-scif", "renesas,scif";
1177 clock-names = "fck", "brg_int", "scif_clk";
1179 dma-names = "tx", "rx";
1180 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1181 resets = <&cpg 203>;
1186 compatible = "renesas,scif-r8a774c0",
1187 "renesas,rcar-gen3-scif", "renesas,scif";
1193 clock-names = "fck", "brg_int", "scif_clk";
1195 dma-names = "tx", "rx";
1196 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1197 resets = <&cpg 202>;
1202 compatible = "renesas,msiof-r8a774c0",
1203 "renesas,rcar-gen3-msiof";
1209 dma-names = "tx", "rx", "tx", "rx";
1210 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1211 resets = <&cpg 211>;
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1218 compatible = "renesas,msiof-r8a774c0",
1219 "renesas,rcar-gen3-msiof";
1224 dma-names = "tx", "rx";
1225 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1226 resets = <&cpg 210>;
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1233 compatible = "renesas,msiof-r8a774c0",
1234 "renesas,rcar-gen3-msiof";
1239 dma-names = "tx", "rx";
1240 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1241 resets = <&cpg 209>;
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1248 compatible = "renesas,msiof-r8a774c0",
1249 "renesas,rcar-gen3-msiof";
1254 dma-names = "tx", "rx";
1255 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1256 resets = <&cpg 208>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1263 compatible = "renesas,vin-r8a774c0";
1267 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1268 resets = <&cpg 807>;
1273 #address-cells = <1>;
1274 #size-cells = <0>;
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1284 remote-endpoint = <&csi40vin4>;
1291 compatible = "renesas,vin-r8a774c0";
1295 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1296 resets = <&cpg 806>;
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1312 remote-endpoint = <&csi40vin5>;
1320 * #sound-dai-cells is required
1322 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1323 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1326 * #clock-cells is required for audio_clkout0/1/2/3
1328 * clkout : #clock-cells = <0>; <&rcar_sound>;
1329 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1331 compatible = "renesas,rcar_sound-r8a774c0",
1332 "renesas,rcar_sound-gen3";
1338 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1357 clock-names = "ssi-all",
1368 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1369 resets = <&cpg 1005>,
1375 reset-names = "ssi-all",
1382 ctu00: ctu-0 { };
1383 ctu01: ctu-1 { };
1384 ctu02: ctu-2 { };
1385 ctu03: ctu-3 { };
1386 ctu10: ctu-4 { };
1387 ctu11: ctu-5 { };
1388 ctu12: ctu-6 { };
1389 ctu13: ctu-7 { };
1393 dvc0: dvc-0 {
1395 dma-names = "tx";
1397 dvc1: dvc-1 {
1399 dma-names = "tx";
1404 mix0: mix-0 { };
1405 mix1: mix-1 { };
1409 src0: src-0 {
1412 dma-names = "rx", "tx";
1414 src1: src-1 {
1417 dma-names = "rx", "tx";
1419 src2: src-2 {
1422 dma-names = "rx", "tx";
1424 src3: src-3 {
1427 dma-names = "rx", "tx";
1429 src4: src-4 {
1432 dma-names = "rx", "tx";
1434 src5: src-5 {
1437 dma-names = "rx", "tx";
1439 src6: src-6 {
1442 dma-names = "rx", "tx";
1444 src7: src-7 {
1447 dma-names = "rx", "tx";
1449 src8: src-8 {
1452 dma-names = "rx", "tx";
1454 src9: src-9 {
1457 dma-names = "rx", "tx";
1462 ssi0: ssi-0 {
1466 dma-names = "rx", "tx", "rxu", "txu";
1468 ssi1: ssi-1 {
1472 dma-names = "rx", "tx", "rxu", "txu";
1474 ssi2: ssi-2 {
1478 dma-names = "rx", "tx", "rxu", "txu";
1480 ssi3: ssi-3 {
1484 dma-names = "rx", "tx", "rxu", "txu";
1486 ssi4: ssi-4 {
1490 dma-names = "rx", "tx", "rxu", "txu";
1492 ssi5: ssi-5 {
1496 dma-names = "rx", "tx", "rxu", "txu";
1498 ssi6: ssi-6 {
1502 dma-names = "rx", "tx", "rxu", "txu";
1504 ssi7: ssi-7 {
1508 dma-names = "rx", "tx", "rxu", "txu";
1510 ssi8: ssi-8 {
1514 dma-names = "rx", "tx", "rxu", "txu";
1516 ssi9: ssi-9 {
1520 dma-names = "rx", "tx", "rxu", "txu";
1525 audma0: dma-controller@ec700000 {
1526 compatible = "renesas,dmac-r8a774c0",
1527 "renesas,rcar-dmac";
1546 interrupt-names = "error",
1552 clock-names = "fck";
1553 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1554 resets = <&cpg 502>;
1555 #dma-cells = <1>;
1556 dma-channels = <16>;
1568 compatible = "renesas,xhci-r8a774c0",
1569 "renesas,rcar-gen3-xhci";
1573 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1574 resets = <&cpg 328>;
1579 compatible = "renesas,r8a774c0-usb3-peri",
1580 "renesas,rcar-gen3-usb3-peri";
1584 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1585 resets = <&cpg 328>;
1590 compatible = "generic-ohci";
1595 phy-names = "usb";
1596 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1597 resets = <&cpg 703>, <&cpg 704>;
1602 compatible = "generic-ehci";
1607 phy-names = "usb";
1609 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1610 resets = <&cpg 703>, <&cpg 704>;
1614 usb2_phy0: usb-phy@ee080200 {
1615 compatible = "renesas,usb2-phy-r8a774c0",
1616 "renesas,rcar-gen3-usb2-phy";
1620 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1621 resets = <&cpg 703>, <&cpg 704>;
1622 #phy-cells = <1>;
1627 compatible = "renesas,sdhi-r8a774c0",
1628 "renesas,rcar-gen3-sdhi";
1632 clock-names = "core", "clkh";
1633 max-frequency = <200000000>;
1634 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1635 resets = <&cpg 314>;
1640 compatible = "renesas,sdhi-r8a774c0",
1641 "renesas,rcar-gen3-sdhi";
1645 clock-names = "core", "clkh";
1646 max-frequency = <200000000>;
1647 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1648 resets = <&cpg 313>;
1653 compatible = "renesas,sdhi-r8a774c0",
1654 "renesas,rcar-gen3-sdhi";
1658 clock-names = "core", "clkh";
1659 max-frequency = <200000000>;
1660 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1661 resets = <&cpg 311>;
1666 compatible = "renesas,r8a774c0-rpc-if",
1667 "renesas,rcar-gen3-rpc-if";
1671 reg-names = "regs", "dirmap", "wbuf";
1674 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1675 resets = <&cpg 917>;
1676 #address-cells = <1>;
1677 #size-cells = <0>;
1681 gic: interrupt-controller@f1010000 {
1682 compatible = "arm,gic-400";
1683 #interrupt-cells = <3>;
1684 #address-cells = <0>;
1685 interrupt-controller;
1693 clock-names = "clk";
1694 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1695 resets = <&cpg 408>;
1699 compatible = "renesas,pcie-r8a774c0",
1700 "renesas,pcie-rcar-gen3";
1702 #address-cells = <3>;
1703 #size-cells = <2>;
1704 bus-range = <0x00 0xff>;
1711 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1715 #interrupt-cells = <1>;
1716 interrupt-map-mask = <0 0 0 0>;
1717 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1719 clock-names = "pcie", "pcie_bus";
1720 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1721 resets = <&cpg 319>;
1725 pciec0_ep: pcie-ep@fe000000 {
1726 compatible = "renesas,r8a774c0-pcie-ep",
1727 "renesas,rcar-gen3-pcie-ep";
1733 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1738 clock-names = "pcie";
1739 resets = <&cpg 319>;
1740 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1749 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1750 resets = <&cpg 626>;
1759 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1760 resets = <&cpg 623>;
1769 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1770 resets = <&cpg 622>;
1779 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1780 resets = <&cpg 631>;
1788 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1789 resets = <&cpg 607>;
1797 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1798 resets = <&cpg 603>;
1806 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1807 resets = <&cpg 602>;
1815 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1816 resets = <&cpg 611>;
1821 compatible = "renesas,r8a774c0-csi2";
1825 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1826 resets = <&cpg 716>;
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1838 #address-cells = <1>;
1839 #size-cells = <0>;
1845 remote-endpoint = <&vin4csi40>;
1849 remote-endpoint = <&vin5csi40>;
1856 compatible = "renesas,du-r8a774c0";
1861 clock-names = "du.0", "du.1";
1862 resets = <&cpg 724>;
1863 reset-names = "du.0";
1869 #address-cells = <1>;
1870 #size-cells = <0>;
1879 remote-endpoint = <&lvds0_in>;
1886 remote-endpoint = <&lvds1_in>;
1892 lvds0: lvds-encoder@feb90000 {
1893 compatible = "renesas,r8a774c0-lvds";
1896 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1897 resets = <&cpg 727>;
1903 #address-cells = <1>;
1904 #size-cells = <0>;
1909 remote-endpoint = <&du_out_lvds0>;
1919 lvds1: lvds-encoder@feb90100 {
1920 compatible = "renesas,r8a774c0-lvds";
1923 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1924 resets = <&cpg 726>;
1928 #address-cells = <1>;
1929 #size-cells = <0>;
1934 remote-endpoint = <&du_out_lvds1>;
1950 thermal-zones {
1951 cpu-thermal {
1952 polling-delay-passive = <250>;
1953 polling-delay = <0>;
1954 thermal-sensors = <&thermal>;
1955 sustainable-power = <717>;
1957 cooling-maps {
1960 cooling-device = <&a53_0 0 2>;
1966 sensor1_crit: sensor1-crit {
1972 target: trip-point1 {
1982 compatible = "arm,armv8-timer";
1983 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1989 /* External USB clocks - can be overridden by the board */
1991 compatible = "fixed-clock";
1992 #clock-cells = <0>;
1993 clock-frequency = <0>;
1997 compatible = "fixed-clock";
1998 #clock-cells = <0>;
1999 clock-frequency = <0>;