Lines Matching +full:0 +full:xe6590630
21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
50 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
76 a57_0: cpu@0 {
78 reg = <0x0>;
91 reg = <0x1>;
100 L2_CA57: cache-controller-0 {
110 #clock-cells = <0>;
112 clock-frequency = <0>;
117 #clock-cells = <0>;
119 clock-frequency = <0>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
144 #clock-cells = <0>;
145 clock-frequency = <0>;
158 reg = <0 0xe6020000 0 0x0c>;
169 reg = <0 0xe6050000 0 0x50>;
173 gpio-ranges = <&pfc 0 0 16>;
184 reg = <0 0xe6051000 0 0x50>;
188 gpio-ranges = <&pfc 0 32 29>;
199 reg = <0 0xe6052000 0 0x50>;
203 gpio-ranges = <&pfc 0 64 15>;
214 reg = <0 0xe6053000 0 0x50>;
218 gpio-ranges = <&pfc 0 96 16>;
229 reg = <0 0xe6054000 0 0x50>;
233 gpio-ranges = <&pfc 0 128 18>;
244 reg = <0 0xe6055000 0 0x50>;
248 gpio-ranges = <&pfc 0 160 26>;
259 reg = <0 0xe6055400 0 0x50>;
263 gpio-ranges = <&pfc 0 192 32>;
274 reg = <0 0xe6055800 0 0x50>;
278 gpio-ranges = <&pfc 0 224 4>;
288 reg = <0 0xe6060000 0 0x50c>;
294 reg = <0 0xe60f0000 0 0x1004>;
307 reg = <0 0xe6130000 0 0x1004>;
326 reg = <0 0xe6140000 0 0x1004>;
345 reg = <0 0xe6148000 0 0x1004>;
363 reg = <0 0xe6150000 0 0x1000>;
367 #power-domain-cells = <0>;
373 reg = <0 0xe6160000 0 0x0200>;
378 reg = <0 0xe6180000 0 0x0400>;
384 reg = <0 0xe6198000 0 0x100>,
385 <0 0xe61a0000 0 0x100>,
386 <0 0xe61a8000 0 0x100>;
400 reg = <0 0xe61c0000 0 0x200>;
401 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
414 reg = <0 0xe61e0000 0 0x30>;
427 reg = <0 0xe6fc0000 0 0x30>;
440 reg = <0 0xe6fd0000 0 0x30>;
453 reg = <0 0xe6fe0000 0 0x30>;
466 reg = <0 0xffc00000 0 0x30>;
479 #size-cells = <0>;
482 reg = <0 0xe6500000 0 0x40>;
487 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
488 <&dmac2 0x91>, <&dmac2 0x90>;
496 #size-cells = <0>;
499 reg = <0 0xe6508000 0 0x40>;
504 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
505 <&dmac2 0x93>, <&dmac2 0x92>;
513 #size-cells = <0>;
516 reg = <0 0xe6510000 0 0x40>;
521 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
522 <&dmac2 0x95>, <&dmac2 0x94>;
530 #size-cells = <0>;
533 reg = <0 0xe66d0000 0 0x40>;
538 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
546 #size-cells = <0>;
549 reg = <0 0xe66d8000 0 0x40>;
554 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
562 #size-cells = <0>;
565 reg = <0 0xe66e0000 0 0x40>;
570 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
578 #size-cells = <0>;
581 reg = <0 0xe66e8000 0 0x40>;
586 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
594 #size-cells = <0>;
598 reg = <0 0xe60b0000 0 0x425>;
603 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
612 reg = <0 0xe6540000 0 0x60>;
618 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
619 <&dmac2 0x31>, <&dmac2 0x30>;
630 reg = <0 0xe6550000 0 0x60>;
636 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
637 <&dmac2 0x33>, <&dmac2 0x32>;
648 reg = <0 0xe6560000 0 0x60>;
654 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
655 <&dmac2 0x35>, <&dmac2 0x34>;
666 reg = <0 0xe66a0000 0 0x60>;
672 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
683 reg = <0 0xe66b0000 0 0x60>;
689 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
699 reg = <0 0xe6590000 0 0x200>;
702 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
703 <&usb_dmac1 0>, <&usb_dmac1 1>;
716 reg = <0 0xe6590630 0 0x02>;
721 #clock-cells = <0>;
731 reg = <0 0xe65a0000 0 0x100>;
745 reg = <0 0xe65b0000 0 0x100>;
759 reg = <0 0xe65ee000 0 0x90>;
765 #phy-cells = <0>;
772 reg = <0 0xe6700000 0 0x10000>;
801 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
814 reg = <0 0xe7300000 0 0x10000>;
843 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
856 reg = <0 0xe7310000 0 0x10000>;
897 reg = <0 0xe6740000 0 0x1000>;
898 renesas,ipmmu-main = <&ipmmu_mm 0>;
905 reg = <0 0xe7740000 0 0x1000>;
913 reg = <0 0xe6570000 0 0x1000>;
921 reg = <0 0xe67b0000 0 0x1000>;
930 reg = <0 0xec670000 0 0x1000>;
938 reg = <0 0xfd800000 0 0x1000>;
946 reg = <0 0xfe6b0000 0 0x1000>;
954 reg = <0 0xfebd0000 0 0x1000>;
962 reg = <0 0xfe990000 0 0x1000>;
971 reg = <0 0xe6800000 0 0x800>;
1009 rx-internal-delay-ps = <0>;
1010 tx-internal-delay-ps = <0>;
1013 #size-cells = <0>;
1020 reg = <0 0xe6c30000 0 0x1000>;
1036 reg = <0 0xe6c38000 0 0x1000>;
1052 reg = <0 0xe66c0000 0 0x8000>;
1077 reg = <0 0xe6e30000 0 0x8>;
1087 reg = <0 0xe6e31000 0 0x8>;
1097 reg = <0 0xe6e32000 0 0x8>;
1107 reg = <0 0xe6e33000 0 0x8>;
1117 reg = <0 0xe6e34000 0 0x8>;
1127 reg = <0 0xe6e35000 0 0x8>;
1137 reg = <0 0xe6e36000 0 0x8>;
1148 reg = <0 0xe6e60000 0 0x40>;
1154 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1155 <&dmac2 0x51>, <&dmac2 0x50>;
1165 reg = <0 0xe6e68000 0 0x40>;
1171 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1172 <&dmac2 0x53>, <&dmac2 0x52>;
1182 reg = <0 0xe6e88000 0 0x40>;
1188 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1189 <&dmac2 0x13>, <&dmac2 0x12>;
1199 reg = <0 0xe6c50000 0 0x40>;
1205 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1215 reg = <0 0xe6c40000 0 0x40>;
1221 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1231 reg = <0 0xe6f30000 0 0x40>;
1237 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1238 <&dmac2 0x5b>, <&dmac2 0x5a>;
1248 reg = <0 0xe6e90000 0 0x0064>;
1251 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1252 <&dmac2 0x41>, <&dmac2 0x40>;
1257 #size-cells = <0>;
1264 reg = <0 0xe6ea0000 0 0x0064>;
1267 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1268 <&dmac2 0x43>, <&dmac2 0x42>;
1273 #size-cells = <0>;
1280 reg = <0 0xe6c00000 0 0x0064>;
1283 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1288 #size-cells = <0>;
1295 reg = <0 0xe6c10000 0 0x0064>;
1298 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1303 #size-cells = <0>;
1309 reg = <0 0xe6ef0000 0 0x1000>;
1314 renesas,id = <0>;
1319 #size-cells = <0>;
1323 #size-cells = <0>;
1327 vin0csi20: endpoint@0 {
1328 reg = <0>;
1341 reg = <0 0xe6ef1000 0 0x1000>;
1351 #size-cells = <0>;
1355 #size-cells = <0>;
1359 vin1csi20: endpoint@0 {
1360 reg = <0>;
1373 reg = <0 0xe6ef2000 0 0x1000>;
1383 #size-cells = <0>;
1387 #size-cells = <0>;
1391 vin2csi20: endpoint@0 {
1392 reg = <0>;
1405 reg = <0 0xe6ef3000 0 0x1000>;
1415 #size-cells = <0>;
1419 #size-cells = <0>;
1423 vin3csi20: endpoint@0 {
1424 reg = <0>;
1437 reg = <0 0xe6ef4000 0 0x1000>;
1447 #size-cells = <0>;
1451 #size-cells = <0>;
1455 vin4csi20: endpoint@0 {
1456 reg = <0>;
1469 reg = <0 0xe6ef5000 0 0x1000>;
1479 #size-cells = <0>;
1483 #size-cells = <0>;
1487 vin5csi20: endpoint@0 {
1488 reg = <0>;
1501 reg = <0 0xe6ef6000 0 0x1000>;
1511 #size-cells = <0>;
1515 #size-cells = <0>;
1519 vin6csi20: endpoint@0 {
1520 reg = <0>;
1533 reg = <0 0xe6ef7000 0 0x1000>;
1543 #size-cells = <0>;
1547 #size-cells = <0>;
1551 vin7csi20: endpoint@0 {
1552 reg = <0>;
1567 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1573 * clkout : #clock-cells = <0>; <&rcar_sound>;
1577 reg = <0 0xec500000 0 0x1000>, /* SCU */
1578 <0 0xec5a0000 0 0x100>, /* ADG */
1579 <0 0xec540000 0 0x1000>, /* SSIU */
1580 <0 0xec541000 0 0x280>, /* SSI */
1581 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1604 "ssi.1", "ssi.0",
1607 "src.1", "src.0",
1608 "mix.1", "mix.0",
1609 "ctu.1", "ctu.0",
1610 "dvc.0", "dvc.1",
1622 "ssi.1", "ssi.0";
1626 ctu00: ctu-0 { };
1637 dvc0: dvc-0 {
1638 dmas = <&audma1 0xbc>;
1642 dmas = <&audma1 0xbe>;
1648 mix0: mix-0 { };
1653 src0: src-0 {
1655 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1660 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1665 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1670 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1675 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1680 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1685 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1690 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1695 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1700 dmas = <&audma0 0x97>, <&audma1 0xba>;
1706 ssi0: ssi-0 {
1708 dmas = <&audma0 0x01>, <&audma1 0x02>;
1713 dmas = <&audma0 0x03>, <&audma1 0x04>;
1718 dmas = <&audma0 0x05>, <&audma1 0x06>;
1723 dmas = <&audma0 0x07>, <&audma1 0x08>;
1728 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1733 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1738 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1743 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1748 dmas = <&audma0 0x11>, <&audma1 0x12>;
1753 dmas = <&audma0 0x13>, <&audma1 0x14>;
1759 ssiu00: ssiu-0 {
1760 dmas = <&audma0 0x15>, <&audma1 0x16>;
1764 dmas = <&audma0 0x35>, <&audma1 0x36>;
1768 dmas = <&audma0 0x37>, <&audma1 0x38>;
1772 dmas = <&audma0 0x47>, <&audma1 0x48>;
1776 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1780 dmas = <&audma0 0x43>, <&audma1 0x44>;
1784 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1788 dmas = <&audma0 0x53>, <&audma1 0x54>;
1792 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1796 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1800 dmas = <&audma0 0x57>, <&audma1 0x58>;
1804 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1808 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1812 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1816 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1820 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1824 dmas = <&audma0 0x63>, <&audma1 0x64>;
1828 dmas = <&audma0 0x67>, <&audma1 0x68>;
1832 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1836 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1840 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1844 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1848 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1852 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1856 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1860 dmas = <&audma0 0x21>, <&audma1 0x22>;
1864 dmas = <&audma0 0x23>, <&audma1 0x24>;
1868 dmas = <&audma0 0x25>, <&audma1 0x26>;
1872 dmas = <&audma0 0x27>, <&audma1 0x28>;
1876 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1880 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1884 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1888 dmas = <&audma0 0x71>, <&audma1 0x72>;
1892 dmas = <&audma0 0x17>, <&audma1 0x18>;
1896 dmas = <&audma0 0x19>, <&audma1 0x1A>;
1900 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
1904 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
1908 dmas = <&audma0 0x1F>, <&audma1 0x20>;
1912 dmas = <&audma0 0x31>, <&audma1 0x32>;
1916 dmas = <&audma0 0x33>, <&audma1 0x34>;
1920 dmas = <&audma0 0x73>, <&audma1 0x74>;
1924 dmas = <&audma0 0x75>, <&audma1 0x76>;
1928 dmas = <&audma0 0x79>, <&audma1 0x7a>;
1932 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
1936 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
1940 dmas = <&audma0 0x7F>, <&audma1 0x80>;
1944 dmas = <&audma0 0x81>, <&audma1 0x82>;
1948 dmas = <&audma0 0x83>, <&audma1 0x84>;
1952 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
1956 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
1960 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
1964 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
1973 reg = <0 0xec700000 0 0x10000>;
2007 reg = <0 0xec720000 0 0x10000>;
2041 reg = <0 0xee000000 0 0xc00>;
2052 reg = <0 0xee020000 0 0x400>;
2062 reg = <0 0xee080000 0 0x100>;
2074 reg = <0 0xee0a0000 0 0x100>;
2086 reg = <0 0xee080100 0 0x100>;
2099 reg = <0 0xee0a0100 0 0x100>;
2113 reg = <0 0xee080200 0 0x700>;
2125 reg = <0 0xee0a0200 0 0x700>;
2136 reg = <0 0xee100000 0 0x2000>;
2149 reg = <0 0xee120000 0 0x2000>;
2162 reg = <0 0xee140000 0 0x2000>;
2175 reg = <0 0xee160000 0 0x2000>;
2188 reg = <0 0xee200000 0 0x200>,
2189 <0 0x08000000 0 0x4000000>,
2190 <0 0xee208000 0 0x100>;
2197 #size-cells = <0>;
2204 reg = <0 0xee300000 0 0x200000>;
2215 #address-cells = <0>;
2217 reg = <0x0 0xf1010000 0 0x1000>,
2218 <0x0 0xf1020000 0 0x20000>,
2219 <0x0 0xf1040000 0 0x20000>,
2220 <0x0 0xf1060000 0 0x20000>;
2232 reg = <0 0xfe000000 0 0x80000>;
2235 bus-range = <0x00 0xff>;
2237 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2238 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2239 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2240 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2242 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2247 interrupt-map-mask = <0 0 0 0>;
2248 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2259 reg = <0 0xee800000 0 0x80000>;
2262 bus-range = <0x00 0xff>;
2264 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2265 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2266 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2267 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2269 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2274 interrupt-map-mask = <0 0 0 0>;
2275 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2286 reg = <0x0 0xfe000000 0 0x80000>,
2287 <0x0 0xfe100000 0 0x100000>,
2288 <0x0 0xfe200000 0 0x200000>,
2289 <0x0 0x30000000 0 0x8000000>,
2290 <0x0 0x38000000 0 0x8000000>;
2305 reg = <0x0 0xee800000 0 0x80000>,
2306 <0x0 0xee900000 0 0x100000>,
2307 <0x0 0xeea00000 0 0x200000>,
2308 <0x0 0xc0000000 0 0x8000000>,
2309 <0x0 0xc8000000 0 0x8000000>;
2323 reg = <0 0xfe940000 0 0x2400>;
2333 reg = <0 0xfe950000 0 0x200>;
2341 reg = <0 0xfe960000 0 0x8000>;
2352 reg = <0 0xfe9a0000 0 0x8000>;
2363 reg = <0 0xfea20000 0 0x5000>;
2374 reg = <0 0xfea28000 0 0x5000>;
2385 reg = <0 0xfe96f000 0 0x200>;
2393 reg = <0 0xfea27000 0 0x200>;
2401 reg = <0 0xfea2f000 0 0x200>;
2409 reg = <0 0xfe9af000 0 0x200>;
2417 reg = <0 0xfea80000 0 0x10000>;
2426 #size-cells = <0>;
2428 port@0 {
2429 reg = <0>;
2434 #size-cells = <0>;
2438 csi20vin0: endpoint@0 {
2439 reg = <0>;
2476 reg = <0 0xfeaa0000 0 0x10000>;
2485 #size-cells = <0>;
2487 port@0 {
2488 reg = <0>;
2493 #size-cells = <0>;
2497 csi40vin0: endpoint@0 {
2498 reg = <0>;
2536 reg = <0 0xfead0000 0 0x10000>;
2547 #size-cells = <0>;
2549 port@0 {
2550 reg = <0>;
2567 reg = <0 0xfeb00000 0 0x80000>;
2573 clock-names = "du.0", "du.1", "du.3";
2575 reset-names = "du.0", "du.3";
2578 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2582 #size-cells = <0>;
2584 port@0 {
2585 reg = <0>;
2604 reg = <0 0xfeb90000 0 0x14>;
2612 #size-cells = <0>;
2614 port@0 {
2615 reg = <0>;
2628 reg = <0 0xfff00044 0 4>;
2636 thermal-sensors = <&tsc 0>;
2672 cooling-device = <&a57_0 0 2>;
2703 #clock-cells = <0>;
2704 clock-frequency = <0>;
2709 #clock-cells = <0>;
2710 clock-frequency = <0>;