Lines Matching +full:i2c +full:- +full:polling
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/interconnect/qcom,sm8450.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
21 #address-cells = <2>;
22 #size-cells = <2>;
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <76800000>;
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32000>;
41 #address-cells = <2>;
42 #size-cells = <0>;
48 enable-method = "psci";
49 next-level-cache = <&L2_0>;
50 power-domains = <&CPU_PD0>;
51 power-domain-names = "psci";
52 qcom,freq-domain = <&cpufreq_hw 0>;
53 #cooling-cells = <2>;
54 L2_0: l2-cache {
56 next-level-cache = <&L3_0>;
57 L3_0: l3-cache {
67 enable-method = "psci";
68 next-level-cache = <&L2_100>;
69 power-domains = <&CPU_PD1>;
70 power-domain-names = "psci";
71 qcom,freq-domain = <&cpufreq_hw 0>;
72 #cooling-cells = <2>;
73 L2_100: l2-cache {
75 next-level-cache = <&L3_0>;
83 enable-method = "psci";
84 next-level-cache = <&L2_200>;
85 power-domains = <&CPU_PD2>;
86 power-domain-names = "psci";
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 #cooling-cells = <2>;
89 L2_200: l2-cache {
91 next-level-cache = <&L3_0>;
99 enable-method = "psci";
100 next-level-cache = <&L2_300>;
101 power-domains = <&CPU_PD3>;
102 power-domain-names = "psci";
103 qcom,freq-domain = <&cpufreq_hw 0>;
104 #cooling-cells = <2>;
105 L2_300: l2-cache {
107 next-level-cache = <&L3_0>;
115 enable-method = "psci";
116 next-level-cache = <&L2_400>;
117 power-domains = <&CPU_PD4>;
118 power-domain-names = "psci";
119 qcom,freq-domain = <&cpufreq_hw 1>;
120 #cooling-cells = <2>;
121 L2_400: l2-cache {
123 next-level-cache = <&L3_0>;
131 enable-method = "psci";
132 next-level-cache = <&L2_500>;
133 power-domains = <&CPU_PD5>;
134 power-domain-names = "psci";
135 qcom,freq-domain = <&cpufreq_hw 1>;
136 #cooling-cells = <2>;
137 L2_500: l2-cache {
139 next-level-cache = <&L3_0>;
148 enable-method = "psci";
149 next-level-cache = <&L2_600>;
150 power-domains = <&CPU_PD6>;
151 power-domain-names = "psci";
152 qcom,freq-domain = <&cpufreq_hw 1>;
153 #cooling-cells = <2>;
154 L2_600: l2-cache {
156 next-level-cache = <&L3_0>;
164 enable-method = "psci";
165 next-level-cache = <&L2_700>;
166 power-domains = <&CPU_PD7>;
167 power-domain-names = "psci";
168 qcom,freq-domain = <&cpufreq_hw 2>;
169 #cooling-cells = <2>;
170 L2_700: l2-cache {
172 next-level-cache = <&L3_0>;
176 cpu-map {
212 idle-states {
213 entry-method = "psci";
215 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
216 compatible = "arm,idle-state";
217 idle-state-name = "silver-rail-power-collapse";
218 arm,psci-suspend-param = <0x40000004>;
219 entry-latency-us = <800>;
220 exit-latency-us = <750>;
221 min-residency-us = <4090>;
222 local-timer-stop;
225 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
226 compatible = "arm,idle-state";
227 idle-state-name = "gold-rail-power-collapse";
228 arm,psci-suspend-param = <0x40000004>;
229 entry-latency-us = <600>;
230 exit-latency-us = <1550>;
231 min-residency-us = <4791>;
232 local-timer-stop;
236 domain-idle-states {
237 CLUSTER_SLEEP_0: cluster-sleep-0 {
238 compatible = "domain-idle-state";
239 idle-state-name = "cluster-l3-off";
240 arm,psci-suspend-param = <0x41000044>;
241 entry-latency-us = <1050>;
242 exit-latency-us = <2500>;
243 min-residency-us = <5309>;
244 local-timer-stop;
247 CLUSTER_SLEEP_1: cluster-sleep-1 {
248 compatible = "domain-idle-state";
249 idle-state-name = "cluster-power-collapse";
250 arm,psci-suspend-param = <0x4100c344>;
251 entry-latency-us = <2700>;
252 exit-latency-us = <3500>;
253 min-residency-us = <13959>;
254 local-timer-stop;
261 compatible = "qcom,scm-sm8450", "qcom,scm";
263 #reset-cells = <1>;
267 clk_virt: interconnect-0 {
268 compatible = "qcom,sm8450-clk-virt";
269 #interconnect-cells = <2>;
270 qcom,bcm-voters = <&apps_bcm_voter>;
273 mc_virt: interconnect-1 {
274 compatible = "qcom,sm8450-mc-virt";
275 #interconnect-cells = <2>;
276 qcom,bcm-voters = <&apps_bcm_voter>;
286 compatible = "arm,armv8-pmuv3";
291 compatible = "arm,psci-1.0";
295 #power-domain-cells = <0>;
296 power-domains = <&CLUSTER_PD>;
297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
301 #power-domain-cells = <0>;
302 power-domains = <&CLUSTER_PD>;
303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
307 #power-domain-cells = <0>;
308 power-domains = <&CLUSTER_PD>;
309 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
313 #power-domain-cells = <0>;
314 power-domains = <&CLUSTER_PD>;
315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
319 #power-domain-cells = <0>;
320 power-domains = <&CLUSTER_PD>;
321 domain-idle-states = <&BIG_CPU_SLEEP_0>;
325 #power-domain-cells = <0>;
326 power-domains = <&CLUSTER_PD>;
327 domain-idle-states = <&BIG_CPU_SLEEP_0>;
331 #power-domain-cells = <0>;
332 power-domains = <&CLUSTER_PD>;
333 domain-idle-states = <&BIG_CPU_SLEEP_0>;
337 #power-domain-cells = <0>;
338 power-domains = <&CLUSTER_PD>;
339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
342 CLUSTER_PD: cpu-cluster0 {
343 #power-domain-cells = <0>;
344 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
348 qup_opp_table_100mhz: opp-table-qup {
349 compatible = "operating-points-v2";
351 opp-50000000 {
352 opp-hz = /bits/ 64 <50000000>;
353 required-opps = <&rpmhpd_opp_min_svs>;
356 opp-75000000 {
357 opp-hz = /bits/ 64 <75000000>;
358 required-opps = <&rpmhpd_opp_low_svs>;
361 opp-100000000 {
362 opp-hz = /bits/ 64 <100000000>;
363 required-opps = <&rpmhpd_opp_svs>;
367 reserved_memory: reserved-memory {
368 #address-cells = <2>;
369 #size-cells = <2>;
374 no-map;
379 no-map;
384 no-map;
389 no-map;
394 no-map;
398 compatible = "qcom,cmd-db";
400 no-map;
405 no-map;
410 no-map;
415 no-map;
420 no-map;
428 no-map;
433 no-map;
438 no-map;
443 no-map;
448 no-map;
453 no-map;
458 no-map;
463 no-map;
468 no-map;
473 no-map;
478 no-map;
484 no-map;
490 no-map;
495 no-map;
500 no-map;
505 no-map;
509 compatible = "qcom,rmtfs-mem";
511 no-map;
513 qcom,client-id = <1>;
519 no-map;
524 no-map;
533 no-map;
538 no-map;
543 no-map;
548 no-map;
553 no-map;
558 no-map;
563 no-map;
568 no-map;
573 no-map;
578 no-map;
583 no-map;
588 no-map;
593 no-map;
598 no-map;
602 smp2p-adsp {
605 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
611 qcom,local-pid = <0>;
612 qcom,remote-pid = <2>;
614 smp2p_adsp_out: master-kernel {
615 qcom,entry-name = "master-kernel";
616 #qcom,smem-state-cells = <1>;
619 smp2p_adsp_in: slave-kernel {
620 qcom,entry-name = "slave-kernel";
621 interrupt-controller;
622 #interrupt-cells = <2>;
626 smp2p-cdsp {
629 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
635 qcom,local-pid = <0>;
636 qcom,remote-pid = <5>;
638 smp2p_cdsp_out: master-kernel {
639 qcom,entry-name = "master-kernel";
640 #qcom,smem-state-cells = <1>;
643 smp2p_cdsp_in: slave-kernel {
644 qcom,entry-name = "slave-kernel";
645 interrupt-controller;
646 #interrupt-cells = <2>;
650 smp2p-modem {
653 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
659 qcom,local-pid = <0>;
660 qcom,remote-pid = <1>;
662 smp2p_modem_out: master-kernel {
663 qcom,entry-name = "master-kernel";
664 #qcom,smem-state-cells = <1>;
667 smp2p_modem_in: slave-kernel {
668 qcom,entry-name = "slave-kernel";
669 interrupt-controller;
670 #interrupt-cells = <2>;
673 ipa_smp2p_out: ipa-ap-to-modem {
674 qcom,entry-name = "ipa";
675 #qcom,smem-state-cells = <1>;
678 ipa_smp2p_in: ipa-modem-to-ap {
679 qcom,entry-name = "ipa";
680 interrupt-controller;
681 #interrupt-cells = <2>;
685 smp2p-slpi {
688 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
694 qcom,local-pid = <0>;
695 qcom,remote-pid = <3>;
697 smp2p_slpi_out: master-kernel {
698 qcom,entry-name = "master-kernel";
699 #qcom,smem-state-cells = <1>;
702 smp2p_slpi_in: slave-kernel {
703 qcom,entry-name = "slave-kernel";
704 interrupt-controller;
705 #interrupt-cells = <2>;
710 #address-cells = <2>;
711 #size-cells = <2>;
713 dma-ranges = <0 0 0 0 0x10 0>;
714 compatible = "simple-bus";
716 gcc: clock-controller@100000 {
717 compatible = "qcom,gcc-sm8450";
719 #clock-cells = <1>;
720 #reset-cells = <1>;
721 #power-domain-cells = <1>;
726 clock-names = "bi_tcxo",
732 gpi_dma2: dma-controller@800000 {
733 compatible = "qcom,sm8450-gpi-dma";
734 #dma-cells = <3>;
748 dma-channels = <12>;
749 dma-channel-mask = <0x7e>;
755 compatible = "qcom,geni-se-qup";
757 clock-names = "m-ahb", "s-ahb";
761 #address-cells = <2>;
762 #size-cells = <2>;
766 i2c15: i2c@880000 {
767 compatible = "qcom,geni-i2c";
769 clock-names = "se";
771 pinctrl-names = "default";
772 pinctrl-0 = <&qup_i2c15_data_clk>;
774 #address-cells = <1>;
775 #size-cells = <0>;
779 interconnect-names = "qup-core", "qup-config", "qup-memory";
782 dma-names = "tx", "rx";
787 compatible = "qcom,geni-spi";
789 clock-names = "se";
792 pinctrl-names = "default";
793 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
794 spi-max-frequency = <50000000>;
797 interconnect-names = "qup-core", "qup-config";
800 dma-names = "tx", "rx";
801 #address-cells = <1>;
802 #size-cells = <0>;
806 i2c16: i2c@884000 {
807 compatible = "qcom,geni-i2c";
809 clock-names = "se";
811 pinctrl-names = "default";
812 pinctrl-0 = <&qup_i2c16_data_clk>;
814 #address-cells = <1>;
815 #size-cells = <0>;
819 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dma-names = "tx", "rx";
827 compatible = "qcom,geni-spi";
829 clock-names = "se";
832 pinctrl-names = "default";
833 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
834 spi-max-frequency = <50000000>;
837 interconnect-names = "qup-core", "qup-config";
840 dma-names = "tx", "rx";
841 #address-cells = <1>;
842 #size-cells = <0>;
846 i2c17: i2c@888000 {
847 compatible = "qcom,geni-i2c";
849 clock-names = "se";
851 pinctrl-names = "default";
852 pinctrl-0 = <&qup_i2c17_data_clk>;
854 #address-cells = <1>;
855 #size-cells = <0>;
859 interconnect-names = "qup-core", "qup-config", "qup-memory";
862 dma-names = "tx", "rx";
867 compatible = "qcom,geni-spi";
869 clock-names = "se";
872 pinctrl-names = "default";
873 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
874 spi-max-frequency = <50000000>;
877 interconnect-names = "qup-core", "qup-config";
880 dma-names = "tx", "rx";
881 #address-cells = <1>;
882 #size-cells = <0>;
886 i2c18: i2c@88c000 {
887 compatible = "qcom,geni-i2c";
889 clock-names = "se";
891 pinctrl-names = "default";
892 pinctrl-0 = <&qup_i2c18_data_clk>;
894 #address-cells = <1>;
895 #size-cells = <0>;
899 interconnect-names = "qup-core", "qup-config", "qup-memory";
902 dma-names = "tx", "rx";
907 compatible = "qcom,geni-spi";
909 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
914 spi-max-frequency = <50000000>;
917 interconnect-names = "qup-core", "qup-config";
920 dma-names = "tx", "rx";
921 #address-cells = <1>;
922 #size-cells = <0>;
926 i2c19: i2c@890000 {
927 compatible = "qcom,geni-i2c";
929 clock-names = "se";
931 pinctrl-names = "default";
932 pinctrl-0 = <&qup_i2c19_data_clk>;
934 #address-cells = <1>;
935 #size-cells = <0>;
939 interconnect-names = "qup-core", "qup-config", "qup-memory";
942 dma-names = "tx", "rx";
947 compatible = "qcom,geni-spi";
949 clock-names = "se";
952 pinctrl-names = "default";
953 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
954 spi-max-frequency = <50000000>;
957 interconnect-names = "qup-core", "qup-config";
960 dma-names = "tx", "rx";
961 #address-cells = <1>;
962 #size-cells = <0>;
966 i2c20: i2c@894000 {
967 compatible = "qcom,geni-i2c";
969 clock-names = "se";
971 pinctrl-names = "default";
972 pinctrl-0 = <&qup_i2c20_data_clk>;
974 #address-cells = <1>;
975 #size-cells = <0>;
979 interconnect-names = "qup-core", "qup-config", "qup-memory";
982 dma-names = "tx", "rx";
987 compatible = "qcom,geni-uart";
989 clock-names = "se";
991 pinctrl-names = "default";
992 pinctrl-0 = <&qup_uart20_default>;
994 #address-cells = <1>;
995 #size-cells = <0>;
1000 compatible = "qcom,geni-spi";
1002 clock-names = "se";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1007 spi-max-frequency = <50000000>;
1010 interconnect-names = "qup-core", "qup-config";
1013 dma-names = "tx", "rx";
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1019 i2c21: i2c@898000 {
1020 compatible = "qcom,geni-i2c";
1022 clock-names = "se";
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&qup_i2c21_data_clk>;
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1032 interconnect-names = "qup-core", "qup-config", "qup-memory";
1035 dma-names = "tx", "rx";
1040 compatible = "qcom,geni-spi";
1042 clock-names = "se";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1047 spi-max-frequency = <50000000>;
1050 interconnect-names = "qup-core", "qup-config";
1053 dma-names = "tx", "rx";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1060 gpi_dma0: dma-controller@900000 {
1061 compatible = "qcom,sm8450-gpi-dma";
1062 #dma-cells = <3>;
1076 dma-channels = <12>;
1077 dma-channel-mask = <0x7e>;
1083 compatible = "qcom,geni-se-qup";
1085 clock-names = "m-ahb", "s-ahb";
1090 interconnect-names = "qup-core";
1091 #address-cells = <2>;
1092 #size-cells = <2>;
1096 i2c0: i2c@980000 {
1097 compatible = "qcom,geni-i2c";
1099 clock-names = "se";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&qup_i2c0_data_clk>;
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1109 interconnect-names = "qup-core", "qup-config", "qup-memory";
1112 dma-names = "tx", "rx";
1117 compatible = "qcom,geni-spi";
1119 clock-names = "se";
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1124 power-domains = <&rpmhpd SM8450_CX>;
1125 operating-points-v2 = <&qup_opp_table_100mhz>;
1129 interconnect-names = "qup-core", "qup-config", "qup-memory";
1132 dma-names = "tx", "rx";
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1138 i2c1: i2c@984000 {
1139 compatible = "qcom,geni-i2c";
1141 clock-names = "se";
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&qup_i2c1_data_clk>;
1146 #address-cells = <1>;
1147 #size-cells = <0>;
1151 interconnect-names = "qup-core", "qup-config", "qup-memory";
1154 dma-names = "tx", "rx";
1159 compatible = "qcom,geni-spi";
1161 clock-names = "se";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1169 interconnect-names = "qup-core", "qup-config", "qup-memory";
1172 dma-names = "tx", "rx";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1178 i2c2: i2c@988000 {
1179 compatible = "qcom,geni-i2c";
1181 clock-names = "se";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&qup_i2c2_data_clk>;
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1191 interconnect-names = "qup-core", "qup-config", "qup-memory";
1194 dma-names = "tx", "rx";
1199 compatible = "qcom,geni-spi";
1201 clock-names = "se";
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1209 interconnect-names = "qup-core", "qup-config", "qup-memory";
1212 dma-names = "tx", "rx";
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1219 i2c3: i2c@98c000 {
1220 compatible = "qcom,geni-i2c";
1222 clock-names = "se";
1224 pinctrl-names = "default";
1225 pinctrl-0 = <&qup_i2c3_data_clk>;
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1232 interconnect-names = "qup-core", "qup-config", "qup-memory";
1235 dma-names = "tx", "rx";
1240 compatible = "qcom,geni-spi";
1242 clock-names = "se";
1245 pinctrl-names = "default";
1246 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1250 interconnect-names = "qup-core", "qup-config", "qup-memory";
1253 dma-names = "tx", "rx";
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1259 i2c4: i2c@990000 {
1260 compatible = "qcom,geni-i2c";
1262 clock-names = "se";
1264 pinctrl-names = "default";
1265 pinctrl-0 = <&qup_i2c4_data_clk>;
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1272 interconnect-names = "qup-core", "qup-config", "qup-memory";
1275 dma-names = "tx", "rx";
1280 compatible = "qcom,geni-spi";
1282 clock-names = "se";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1287 power-domains = <&rpmhpd SM8450_CX>;
1288 operating-points-v2 = <&qup_opp_table_100mhz>;
1292 interconnect-names = "qup-core", "qup-config", "qup-memory";
1295 dma-names = "tx", "rx";
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1301 i2c5: i2c@994000 {
1302 compatible = "qcom,geni-i2c";
1304 clock-names = "se";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&qup_i2c5_data_clk>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1314 interconnect-names = "qup-core", "qup-config", "qup-memory";
1317 dma-names = "tx", "rx";
1322 compatible = "qcom,geni-spi";
1324 clock-names = "se";
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1332 interconnect-names = "qup-core", "qup-config", "qup-memory";
1335 dma-names = "tx", "rx";
1336 #address-cells = <1>;
1337 #size-cells = <0>;
1342 i2c6: i2c@998000 {
1343 compatible = "qcom,geni-i2c";
1345 clock-names = "se";
1347 pinctrl-names = "default";
1348 pinctrl-0 = <&qup_i2c6_data_clk>;
1350 #address-cells = <1>;
1351 #size-cells = <0>;
1355 interconnect-names = "qup-core", "qup-config", "qup-memory";
1358 dma-names = "tx", "rx";
1363 compatible = "qcom,geni-spi";
1365 clock-names = "se";
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1373 interconnect-names = "qup-core", "qup-config", "qup-memory";
1376 dma-names = "tx", "rx";
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1383 compatible = "qcom,geni-debug-uart";
1385 clock-names = "se";
1387 pinctrl-names = "default";
1388 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1396 gpi_dma1: dma-controller@a00000 {
1397 compatible = "qcom,sm8450-gpi-dma";
1398 #dma-cells = <3>;
1412 dma-channels = <12>;
1413 dma-channel-mask = <0x7e>;
1419 compatible = "qcom,geni-se-qup";
1421 clock-names = "m-ahb", "s-ahb";
1426 interconnect-names = "qup-core";
1427 #address-cells = <2>;
1428 #size-cells = <2>;
1432 i2c8: i2c@a80000 {
1433 compatible = "qcom,geni-i2c";
1435 clock-names = "se";
1437 pinctrl-names = "default";
1438 pinctrl-0 = <&qup_i2c8_data_clk>;
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1445 interconnect-names = "qup-core", "qup-config", "qup-memory";
1448 dma-names = "tx", "rx";
1453 compatible = "qcom,geni-spi";
1455 clock-names = "se";
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1463 interconnect-names = "qup-core", "qup-config", "qup-memory";
1466 dma-names = "tx", "rx";
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1472 i2c9: i2c@a84000 {
1473 compatible = "qcom,geni-i2c";
1475 clock-names = "se";
1477 pinctrl-names = "default";
1478 pinctrl-0 = <&qup_i2c9_data_clk>;
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1485 interconnect-names = "qup-core", "qup-config", "qup-memory";
1488 dma-names = "tx", "rx";
1493 compatible = "qcom,geni-spi";
1495 clock-names = "se";
1498 pinctrl-names = "default";
1499 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1503 interconnect-names = "qup-core", "qup-config", "qup-memory";
1506 dma-names = "tx", "rx";
1507 #address-cells = <1>;
1508 #size-cells = <0>;
1512 i2c10: i2c@a88000 {
1513 compatible = "qcom,geni-i2c";
1515 clock-names = "se";
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_i2c10_data_clk>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1525 interconnect-names = "qup-core", "qup-config", "qup-memory";
1528 dma-names = "tx", "rx";
1533 compatible = "qcom,geni-spi";
1535 clock-names = "se";
1538 pinctrl-names = "default";
1539 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1543 interconnect-names = "qup-core", "qup-config", "qup-memory";
1546 dma-names = "tx", "rx";
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1552 i2c11: i2c@a8c000 {
1553 compatible = "qcom,geni-i2c";
1555 clock-names = "se";
1557 pinctrl-names = "default";
1558 pinctrl-0 = <&qup_i2c11_data_clk>;
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1565 interconnect-names = "qup-core", "qup-config", "qup-memory";
1568 dma-names = "tx", "rx";
1573 compatible = "qcom,geni-spi";
1575 clock-names = "se";
1578 pinctrl-names = "default";
1579 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1583 interconnect-names = "qup-core", "qup-config", "qup-memory";
1586 dma-names = "tx", "rx";
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1592 i2c12: i2c@a90000 {
1593 compatible = "qcom,geni-i2c";
1595 clock-names = "se";
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_i2c12_data_clk>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1605 interconnect-names = "qup-core", "qup-config", "qup-memory";
1608 dma-names = "tx", "rx";
1613 compatible = "qcom,geni-spi";
1615 clock-names = "se";
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1626 dma-names = "tx", "rx";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1632 i2c13: i2c@a94000 {
1633 compatible = "qcom,geni-i2c";
1635 clock-names = "se";
1637 pinctrl-names = "default";
1638 pinctrl-0 = <&qup_i2c13_data_clk>;
1643 interconnect-names = "qup-core", "qup-config", "qup-memory";
1646 dma-names = "tx", "rx";
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1653 compatible = "qcom,geni-spi";
1655 clock-names = "se";
1658 pinctrl-names = "default";
1659 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1663 interconnect-names = "qup-core", "qup-config", "qup-memory";
1666 dma-names = "tx", "rx";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1672 i2c14: i2c@a98000 {
1673 compatible = "qcom,geni-i2c";
1675 clock-names = "se";
1677 pinctrl-names = "default";
1678 pinctrl-0 = <&qup_i2c14_data_clk>;
1683 interconnect-names = "qup-core", "qup-config", "qup-memory";
1686 dma-names = "tx", "rx";
1687 #address-cells = <1>;
1688 #size-cells = <0>;
1693 compatible = "qcom,geni-spi";
1695 clock-names = "se";
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1703 interconnect-names = "qup-core", "qup-config", "qup-memory";
1706 dma-names = "tx", "rx";
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1714 compatible = "qcom,pcie-sm8450-pcie0";
1720 reg-names = "parf", "dbi", "elbi", "atu", "config";
1722 linux,pci-domain = <0>;
1723 bus-range = <0x00 0xff>;
1724 num-lanes = <1>;
1726 #address-cells = <3>;
1727 #size-cells = <2>;
1733 interrupt-names = "msi";
1734 #interrupt-cells = <1>;
1735 interrupt-map-mask = <0 0 0 0x7>;
1736 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1753 clock-names = "pipe",
1767 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1771 reset-names = "pci";
1773 power-domains = <&gcc PCIE_0_GDSC>;
1774 power-domain-names = "gdsc";
1777 phy-names = "pciephy";
1779 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1780 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1782 pinctrl-names = "default";
1783 pinctrl-0 = <&pcie0_default_state>;
1789 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1791 #address-cells = <2>;
1792 #size-cells = <2>;
1798 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1801 reset-names = "phy";
1803 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1804 assigned-clock-rates = <100000000>;
1814 clock-names = "pipe0";
1816 #clock-cells = <0>;
1817 #phy-cells = <0>;
1818 clock-output-names = "pcie_0_pipe_clk";
1823 compatible = "qcom,pcie-sm8450-pcie1";
1829 reg-names = "parf", "dbi", "elbi", "atu", "config";
1831 linux,pci-domain = <1>;
1832 bus-range = <0x00 0xff>;
1833 num-lanes = <2>;
1835 #address-cells = <3>;
1836 #size-cells = <2>;
1842 interrupt-names = "msi";
1843 #interrupt-cells = <1>;
1844 interrupt-map-mask = <0 0 0 0x7>;
1845 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1861 clock-names = "pipe",
1874 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1878 reset-names = "pci";
1880 power-domains = <&gcc PCIE_1_GDSC>;
1881 power-domain-names = "gdsc";
1884 phy-names = "pciephy";
1886 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>;
1887 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1889 pinctrl-names = "default";
1890 pinctrl-0 = <&pcie1_default_state>;
1896 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1898 #address-cells = <2>;
1899 #size-cells = <2>;
1905 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1908 reset-names = "phy";
1910 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1911 assigned-clock-rates = <100000000>;
1923 clock-names = "pipe0";
1925 #clock-cells = <0>;
1926 #phy-cells = <0>;
1927 clock-output-names = "pcie_1_pipe_clk";
1932 compatible = "qcom,sm8450-config-noc";
1934 #interconnect-cells = <2>;
1935 qcom,bcm-voters = <&apps_bcm_voter>;
1939 compatible = "qcom,sm8450-system-noc";
1941 #interconnect-cells = <2>;
1942 qcom,bcm-voters = <&apps_bcm_voter>;
1946 compatible = "qcom,sm8450-pcie-anoc";
1948 #interconnect-cells = <2>;
1949 qcom,bcm-voters = <&apps_bcm_voter>;
1953 compatible = "qcom,sm8450-aggre1-noc";
1955 #interconnect-cells = <2>;
1958 qcom,bcm-voters = <&apps_bcm_voter>;
1962 compatible = "qcom,sm8450-aggre2-noc";
1964 #interconnect-cells = <2>;
1965 qcom,bcm-voters = <&apps_bcm_voter>;
1973 compatible = "qcom,sm8450-mmss-noc";
1975 #interconnect-cells = <2>;
1976 qcom,bcm-voters = <&apps_bcm_voter>;
1980 compatible = "qcom,tcsr-mutex";
1982 #hwlock-cells = <1>;
1986 compatible = "qcom,sm8450-usb-hs-phy",
1987 "qcom,usb-snps-hs-7nm-phy";
1990 #phy-cells = <0>;
1993 clock-names = "ref";
1998 usb_1_qmpphy: phy-wrapper@88e9000 {
1999 compatible = "qcom,sm8450-qmp-usb3-phy";
2003 #address-cells = <2>;
2004 #size-cells = <2>;
2010 clock-names = "aux", "ref_clk_src", "com_aux";
2014 reset-names = "phy", "common";
2023 #phy-cells = <0>;
2024 #clock-cells = <0>;
2026 clock-names = "pipe0";
2027 clock-output-names = "usb3_phy_pipe_clk_src";
2032 compatible = "qcom,sm8450-slpi-pas";
2035 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2040 interrupt-names = "wdog", "fatal", "ready",
2041 "handover", "stop-ack";
2044 clock-names = "xo";
2046 power-domains = <&rpmhpd SM8450_LCX>,
2048 power-domain-names = "lcx", "lmx";
2050 memory-region = <&slpi_mem>;
2054 qcom,smem-states = <&smp2p_slpi_out 0>;
2055 qcom,smem-state-names = "stop";
2059 glink-edge {
2060 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2067 qcom,remote-pid = <3>;
2071 qcom,glink-channels = "fastrpcglink-apps-dsp";
2073 #address-cells = <1>;
2074 #size-cells = <0>;
2076 compute-cb@1 {
2077 compatible = "qcom,fastrpc-compute-cb";
2082 compute-cb@2 {
2083 compatible = "qcom,fastrpc-compute-cb";
2088 compute-cb@3 {
2089 compatible = "qcom,fastrpc-compute-cb";
2092 /* note: shared-cb = <4> in downstream */
2099 compatible = "qcom,sm8450-adsp-pas";
2102 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2107 interrupt-names = "wdog", "fatal", "ready",
2108 "handover", "stop-ack";
2111 clock-names = "xo";
2113 power-domains = <&rpmhpd SM8450_LCX>,
2115 power-domain-names = "lcx", "lmx";
2117 memory-region = <&adsp_mem>;
2121 qcom,smem-states = <&smp2p_adsp_out 0>;
2122 qcom,smem-state-names = "stop";
2126 remoteproc_adsp_glink: glink-edge {
2127 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2134 qcom,remote-pid = <2>;
2138 qcom,glink-channels = "fastrpcglink-apps-dsp";
2140 #address-cells = <1>;
2141 #size-cells = <0>;
2143 compute-cb@3 {
2144 compatible = "qcom,fastrpc-compute-cb";
2149 compute-cb@4 {
2150 compatible = "qcom,fastrpc-compute-cb";
2155 compute-cb@5 {
2156 compatible = "qcom,fastrpc-compute-cb";
2165 compatible = "qcom,sm8450-cdsp-pas";
2168 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2173 interrupt-names = "wdog", "fatal", "ready",
2174 "handover", "stop-ack";
2177 clock-names = "xo";
2179 power-domains = <&rpmhpd SM8450_CX>,
2181 power-domain-names = "cx", "mxc";
2183 memory-region = <&cdsp_mem>;
2187 qcom,smem-states = <&smp2p_cdsp_out 0>;
2188 qcom,smem-state-names = "stop";
2192 glink-edge {
2193 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2200 qcom,remote-pid = <5>;
2204 qcom,glink-channels = "fastrpcglink-apps-dsp";
2206 #address-cells = <1>;
2207 #size-cells = <0>;
2209 compute-cb@1 {
2210 compatible = "qcom,fastrpc-compute-cb";
2216 compute-cb@2 {
2217 compatible = "qcom,fastrpc-compute-cb";
2223 compute-cb@3 {
2224 compatible = "qcom,fastrpc-compute-cb";
2230 compute-cb@4 {
2231 compatible = "qcom,fastrpc-compute-cb";
2237 compute-cb@5 {
2238 compatible = "qcom,fastrpc-compute-cb";
2244 compute-cb@6 {
2245 compatible = "qcom,fastrpc-compute-cb";
2251 compute-cb@7 {
2252 compatible = "qcom,fastrpc-compute-cb";
2258 compute-cb@8 {
2259 compatible = "qcom,fastrpc-compute-cb";
2271 compatible = "qcom,sm8450-mpss-pas";
2274 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2280 interrupt-names = "wdog", "fatal", "ready", "handover",
2281 "stop-ack", "shutdown-ack";
2284 clock-names = "xo";
2286 power-domains = <&rpmhpd 0>,
2288 power-domain-names = "cx", "mss";
2290 memory-region = <&mpss_mem>;
2294 qcom,smem-states = <&smp2p_modem_out 0>;
2295 qcom,smem-state-names = "stop";
2299 glink-edge {
2300 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2306 qcom,remote-pid = <1>;
2310 camcc: clock-controller@ade0000 {
2311 compatible = "qcom,sm8450-camcc";
2317 power-domains = <&rpmhpd SM8450_MMCX>;
2318 required-opps = <&rpmhpd_opp_low_svs>;
2319 #clock-cells = <1>;
2320 #reset-cells = <1>;
2321 #power-domain-cells = <1>;
2325 pdc: interrupt-controller@b220000 {
2326 compatible = "qcom,sm8450-pdc", "qcom,pdc";
2328 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
2330 #interrupt-cells = <2>;
2331 interrupt-parent = <&intc>;
2332 interrupt-controller;
2335 tsens0: thermal-sensor@c263000 {
2336 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
2342 interrupt-names = "uplow", "critical";
2343 #thermal-sensor-cells = <1>;
2346 tsens1: thermal-sensor@c265000 {
2347 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
2353 interrupt-names = "uplow", "critical";
2354 #thermal-sensor-cells = <1>;
2357 aoss_qmp: power-controller@c300000 {
2358 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
2360 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2364 #clock-cells = <0>;
2368 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
2371 interrupt-controller;
2372 #interrupt-cells = <3>;
2373 #mbox-cells = <2>;
2377 compatible = "qcom,sm8450-tlmm";
2380 gpio-controller;
2381 #gpio-cells = <2>;
2382 interrupt-controller;
2383 #interrupt-cells = <2>;
2384 gpio-ranges = <&tlmm 0 0 211>;
2385 wakeup-parent = <&pdc>;
2387 sdc2_sleep_state: sdc2-sleep-state {
2388 clk-pins {
2390 drive-strength = <2>;
2391 bias-disable;
2394 cmd-pins {
2396 drive-strength = <2>;
2397 bias-pull-up;
2400 data-pins {
2402 drive-strength = <2>;
2403 bias-pull-up;
2407 pcie0_default_state: pcie0-default-state {
2408 perst-pins {
2411 drive-strength = <2>;
2412 bias-pull-down;
2415 clkreq-pins {
2418 drive-strength = <2>;
2419 bias-pull-up;
2422 wake-pins {
2425 drive-strength = <2>;
2426 bias-pull-up;
2430 pcie1_default_state: pcie1-default-state {
2431 perst-pins {
2434 drive-strength = <2>;
2435 bias-pull-down;
2438 clkreq-pins {
2441 drive-strength = <2>;
2442 bias-pull-up;
2445 wake-pins {
2448 drive-strength = <2>;
2449 bias-pull-up;
2453 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
2458 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
2463 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
2468 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
2473 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
2478 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
2483 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
2488 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
2493 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
2498 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
2503 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
2508 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
2513 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
2516 drive-strength = <2>;
2517 bias-pull-up;
2520 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
2523 drive-strength = <2>;
2524 bias-pull-up;
2527 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
2532 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
2537 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
2542 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
2547 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
2552 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
2557 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
2562 qup_spi0_cs: qup-spi0-cs-state {
2567 qup_spi0_data_clk: qup-spi0-data-clk-state {
2572 qup_spi1_cs: qup-spi1-cs-state {
2577 qup_spi1_data_clk: qup-spi1-data-clk-state {
2582 qup_spi2_cs: qup-spi2-cs-state {
2587 qup_spi2_data_clk: qup-spi2-data-clk-state {
2592 qup_spi3_cs: qup-spi3-cs-state {
2597 qup_spi3_data_clk: qup-spi3-data-clk-state {
2602 qup_spi4_cs: qup-spi4-cs-state {
2605 drive-strength = <6>;
2606 bias-disable;
2609 qup_spi4_data_clk: qup-spi4-data-clk-state {
2614 qup_spi5_cs: qup-spi5-cs-state {
2619 qup_spi5_data_clk: qup-spi5-data-clk-state {
2624 qup_spi6_cs: qup-spi6-cs-state {
2629 qup_spi6_data_clk: qup-spi6-data-clk-state {
2634 qup_spi8_cs: qup-spi8-cs-state {
2639 qup_spi8_data_clk: qup-spi8-data-clk-state {
2644 qup_spi9_cs: qup-spi9-cs-state {
2649 qup_spi9_data_clk: qup-spi9-data-clk-state {
2654 qup_spi10_cs: qup-spi10-cs-state {
2659 qup_spi10_data_clk: qup-spi10-data-clk-state {
2664 qup_spi11_cs: qup-spi11-cs-state {
2669 qup_spi11_data_clk: qup-spi11-data-clk-state {
2674 qup_spi12_cs: qup-spi12-cs-state {
2679 qup_spi12_data_clk: qup-spi12-data-clk-state {
2684 qup_spi13_cs: qup-spi13-cs-state {
2689 qup_spi13_data_clk: qup-spi13-data-clk-state {
2694 qup_spi14_cs: qup-spi14-cs-state {
2699 qup_spi14_data_clk: qup-spi14-data-clk-state {
2704 qup_spi15_cs: qup-spi15-cs-state {
2709 qup_spi15_data_clk: qup-spi15-data-clk-state {
2714 qup_spi16_cs: qup-spi16-cs-state {
2719 qup_spi16_data_clk: qup-spi16-data-clk-state {
2724 qup_spi17_cs: qup-spi17-cs-state {
2729 qup_spi17_data_clk: qup-spi17-data-clk-state {
2734 qup_spi18_cs: qup-spi18-cs-state {
2737 drive-strength = <6>;
2738 bias-disable;
2741 qup_spi18_data_clk: qup-spi18-data-clk-state {
2744 drive-strength = <6>;
2745 bias-disable;
2748 qup_spi19_cs: qup-spi19-cs-state {
2751 drive-strength = <6>;
2752 bias-disable;
2755 qup_spi19_data_clk: qup-spi19-data-clk-state {
2758 drive-strength = <6>;
2759 bias-disable;
2762 qup_spi20_cs: qup-spi20-cs-state {
2767 qup_spi20_data_clk: qup-spi20-data-clk-state {
2772 qup_spi21_cs: qup-spi21-cs-state {
2777 qup_spi21_data_clk: qup-spi21-data-clk-state {
2782 qup_uart7_rx: qup-uart7-rx-state {
2785 drive-strength = <2>;
2786 bias-disable;
2789 qup_uart7_tx: qup-uart7-tx-state {
2792 drive-strength = <2>;
2793 bias-disable;
2796 qup_uart20_default: qup-uart20-default-state {
2804 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
2806 #iommu-cells = <2>;
2807 #global-interrupts = <1>;
2907 intc: interrupt-controller@17100000 {
2908 compatible = "arm,gic-v3";
2909 #interrupt-cells = <3>;
2910 interrupt-controller;
2911 #redistributor-regions = <1>;
2912 redistributor-stride = <0x0 0x40000>;
2916 #address-cells = <2>;
2917 #size-cells = <2>;
2920 gic_its: msi-controller@17140000 {
2921 compatible = "arm,gic-v3-its";
2923 msi-controller;
2924 #msi-cells = <1>;
2929 compatible = "arm,armv7-timer-mem";
2930 #address-cells = <1>;
2931 #size-cells = <1>;
2934 clock-frequency = <19200000>;
2937 frame-number = <0>;
2945 frame-number = <1>;
2952 frame-number = <2>;
2959 frame-number = <3>;
2966 frame-number = <4>;
2973 frame-number = <5>;
2980 frame-number = <6>;
2989 compatible = "qcom,rpmh-rsc";
2994 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
2998 qcom,tcs-offset = <0xd00>;
2999 qcom,drv-id = <2>;
3000 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3003 apps_bcm_voter: bcm-voter {
3004 compatible = "qcom,bcm-voter";
3007 rpmhcc: clock-controller {
3008 compatible = "qcom,sm8450-rpmh-clk";
3009 #clock-cells = <1>;
3010 clock-names = "xo";
3014 rpmhpd: power-controller {
3015 compatible = "qcom,sm8450-rpmhpd";
3016 #power-domain-cells = <1>;
3017 operating-points-v2 = <&rpmhpd_opp_table>;
3019 rpmhpd_opp_table: opp-table {
3020 compatible = "operating-points-v2";
3023 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3027 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3031 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3035 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3039 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3043 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3047 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3051 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3055 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3059 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3066 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
3070 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3072 clock-names = "xo", "alternate";
3076 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3077 #freq-domain-cells = <1>;
3081 compatible = "qcom,sm8450-gem-noc";
3083 #interconnect-cells = <2>;
3084 qcom,bcm-voters = <&apps_bcm_voter>;
3087 system-cache-controller@19200000 {
3088 compatible = "qcom,sm8450-llcc";
3090 reg-names = "llcc_base", "llcc_broadcast_base";
3095 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
3096 "jedec,ufs-2.0";
3099 reg-names = "std", "ice";
3102 phy-names = "ufsphy";
3103 lanes-per-direction = <2>;
3104 #reset-cells = <1>;
3106 reset-names = "rst";
3108 power-domains = <&gcc UFS_PHY_GDSC>;
3114 interconnect-names = "ufs-ddr", "cpu-ufs";
3115 clock-names =
3135 freq-table-hz =
3149 compatible = "qcom,sm8450-qmp-ufs-phy";
3151 #address-cells = <2>;
3152 #size-cells = <2>;
3154 clock-names = "ref", "ref_aux", "qref";
3160 reset-names = "ufsphy";
3169 #phy-cells = <0>;
3174 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
3179 interrupt-names = "hc_irq", "pwr_irq";
3184 clock-names = "iface", "core", "xo";
3188 interconnect-names = "sdhc-ddr","cpu-sdhc";
3190 power-domains = <&rpmhpd SM8450_CX>;
3191 operating-points-v2 = <&sdhc2_opp_table>;
3192 bus-width = <4>;
3193 dma-coherent;
3197 sdhc2_opp_table: opp-table {
3198 compatible = "operating-points-v2";
3200 opp-100000000 {
3201 opp-hz = /bits/ 64 <100000000>;
3202 required-opps = <&rpmhpd_opp_low_svs>;
3205 opp-202000000 {
3206 opp-hz = /bits/ 64 <202000000>;
3207 required-opps = <&rpmhpd_opp_svs_l1>;
3213 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
3216 #address-cells = <2>;
3217 #size-cells = <2>;
3226 clock-names = "cfg_noc",
3233 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3235 assigned-clock-rates = <19200000>, <200000000>;
3237 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3241 interrupt-names = "hs_phy_irq",
3246 power-domains = <&gcc USB30_PRIM_GDSC>;
3258 phy-names = "usb2-phy", "usb3-phy";
3263 compatible = "qcom,sm8450-nsp-noc";
3265 #interconnect-cells = <2>;
3266 qcom,bcm-voters = <&apps_bcm_voter>;
3270 compatible = "qcom,sm8450-lpass-ag-noc";
3272 #interconnect-cells = <2>;
3273 qcom,bcm-voters = <&apps_bcm_voter>;
3277 thermal-zones {
3278 aoss0-thermal {
3279 polling-delay-passive = <0>;
3280 polling-delay = <0>;
3281 thermal-sensors = <&tsens0 0>;
3284 thermal-engine-config {
3290 reset-mon-cfg {
3298 cpuss0-thermal {
3299 polling-delay-passive = <0>;
3300 polling-delay = <0>;
3301 thermal-sensors = <&tsens0 1>;
3304 thermal-engine-config {
3310 reset-mon-cfg {
3318 cpuss1-thermal {
3319 polling-delay-passive = <0>;
3320 polling-delay = <0>;
3321 thermal-sensors = <&tsens0 2>;
3324 thermal-engine-config {
3330 reset-mon-cfg {
3338 cpuss3-thermal {
3339 polling-delay-passive = <0>;
3340 polling-delay = <0>;
3341 thermal-sensors = <&tsens0 3>;
3344 thermal-engine-config {
3350 reset-mon-cfg {
3358 cpuss4-thermal {
3359 polling-delay-passive = <0>;
3360 polling-delay = <0>;
3361 thermal-sensors = <&tsens0 4>;
3364 thermal-engine-config {
3370 reset-mon-cfg {
3378 cpu4-top-thermal {
3379 polling-delay-passive = <0>;
3380 polling-delay = <0>;
3381 thermal-sensors = <&tsens0 5>;
3384 cpu4_top_alert0: trip-point0 {
3390 cpu4_top_alert1: trip-point1 {
3404 cpu4-bottom-thermal {
3405 polling-delay-passive = <0>;
3406 polling-delay = <0>;
3407 thermal-sensors = <&tsens0 6>;
3410 cpu4_bottom_alert0: trip-point0 {
3416 cpu4_bottom_alert1: trip-point1 {
3430 cpu5-top-thermal {
3431 polling-delay-passive = <0>;
3432 polling-delay = <0>;
3433 thermal-sensors = <&tsens0 7>;
3436 cpu5_top_alert0: trip-point0 {
3442 cpu5_top_alert1: trip-point1 {
3456 cpu5-bottom-thermal {
3457 polling-delay-passive = <0>;
3458 polling-delay = <0>;
3459 thermal-sensors = <&tsens0 8>;
3462 cpu5_bottom_alert0: trip-point0 {
3468 cpu5_bottom_alert1: trip-point1 {
3482 cpu6-top-thermal {
3483 polling-delay-passive = <0>;
3484 polling-delay = <0>;
3485 thermal-sensors = <&tsens0 9>;
3488 cpu6_top_alert0: trip-point0 {
3494 cpu6_top_alert1: trip-point1 {
3508 cpu6-bottom-thermal {
3509 polling-delay-passive = <0>;
3510 polling-delay = <0>;
3511 thermal-sensors = <&tsens0 10>;
3514 cpu6_bottom_alert0: trip-point0 {
3520 cpu6_bottom_alert1: trip-point1 {
3534 cpu7-top-thermal {
3535 polling-delay-passive = <0>;
3536 polling-delay = <0>;
3537 thermal-sensors = <&tsens0 11>;
3540 cpu7_top_alert0: trip-point0 {
3546 cpu7_top_alert1: trip-point1 {
3560 cpu7-middle-thermal {
3561 polling-delay-passive = <0>;
3562 polling-delay = <0>;
3563 thermal-sensors = <&tsens0 12>;
3566 cpu7_middle_alert0: trip-point0 {
3572 cpu7_middle_alert1: trip-point1 {
3586 cpu7-bottom-thermal {
3587 polling-delay-passive = <0>;
3588 polling-delay = <0>;
3589 thermal-sensors = <&tsens0 13>;
3592 cpu7_bottom_alert0: trip-point0 {
3598 cpu7_bottom_alert1: trip-point1 {
3612 gpu-top-thermal {
3613 polling-delay-passive = <10>;
3614 polling-delay = <0>;
3615 thermal-sensors = <&tsens0 14>;
3618 thermal-engine-config {
3624 thermal-hal-config {
3630 reset-mon-cfg {
3644 gpu-bottom-thermal {
3645 polling-delay-passive = <10>;
3646 polling-delay = <0>;
3647 thermal-sensors = <&tsens0 15>;
3650 thermal-engine-config {
3656 thermal-hal-config {
3662 reset-mon-cfg {
3676 aoss1-thermal {
3677 polling-delay-passive = <0>;
3678 polling-delay = <0>;
3679 thermal-sensors = <&tsens1 0>;
3682 thermal-engine-config {
3688 reset-mon-cfg {
3696 cpu0-thermal {
3697 polling-delay-passive = <0>;
3698 polling-delay = <0>;
3699 thermal-sensors = <&tsens1 1>;
3702 cpu0_alert0: trip-point0 {
3708 cpu0_alert1: trip-point1 {
3722 cpu1-thermal {
3723 polling-delay-passive = <0>;
3724 polling-delay = <0>;
3725 thermal-sensors = <&tsens1 2>;
3728 cpu1_alert0: trip-point0 {
3734 cpu1_alert1: trip-point1 {
3748 cpu2-thermal {
3749 polling-delay-passive = <0>;
3750 polling-delay = <0>;
3751 thermal-sensors = <&tsens1 3>;
3754 cpu2_alert0: trip-point0 {
3760 cpu2_alert1: trip-point1 {
3774 cpu3-thermal {
3775 polling-delay-passive = <0>;
3776 polling-delay = <0>;
3777 thermal-sensors = <&tsens1 4>;
3780 cpu3_alert0: trip-point0 {
3786 cpu3_alert1: trip-point1 {
3800 cdsp0-thermal {
3801 polling-delay-passive = <10>;
3802 polling-delay = <0>;
3803 thermal-sensors = <&tsens1 5>;
3806 thermal-engine-config {
3812 thermal-hal-config {
3818 reset-mon-cfg {
3824 cdsp_0_config: junction-config {
3832 cdsp1-thermal {
3833 polling-delay-passive = <10>;
3834 polling-delay = <0>;
3835 thermal-sensors = <&tsens1 6>;
3838 thermal-engine-config {
3844 thermal-hal-config {
3850 reset-mon-cfg {
3856 cdsp_1_config: junction-config {
3864 cdsp2-thermal {
3865 polling-delay-passive = <10>;
3866 polling-delay = <0>;
3867 thermal-sensors = <&tsens1 7>;
3870 thermal-engine-config {
3876 thermal-hal-config {
3882 reset-mon-cfg {
3888 cdsp_2_config: junction-config {
3896 video-thermal {
3897 polling-delay-passive = <0>;
3898 polling-delay = <0>;
3899 thermal-sensors = <&tsens1 8>;
3902 thermal-engine-config {
3908 reset-mon-cfg {
3916 mem-thermal {
3917 polling-delay-passive = <10>;
3918 polling-delay = <0>;
3919 thermal-sensors = <&tsens1 9>;
3922 thermal-engine-config {
3928 ddr_config0: ddr0-config {
3934 reset-mon-cfg {
3942 modem0-thermal {
3943 polling-delay-passive = <0>;
3944 polling-delay = <0>;
3945 thermal-sensors = <&tsens1 10>;
3948 thermal-engine-config {
3954 mdmss0_config0: mdmss0-config0 {
3960 mdmss0_config1: mdmss0-config1 {
3966 reset-mon-cfg {
3974 modem1-thermal {
3975 polling-delay-passive = <0>;
3976 polling-delay = <0>;
3977 thermal-sensors = <&tsens1 11>;
3980 thermal-engine-config {
3986 mdmss1_config0: mdmss1-config0 {
3992 mdmss1_config1: mdmss1-config1 {
3998 reset-mon-cfg {
4006 modem2-thermal {
4007 polling-delay-passive = <0>;
4008 polling-delay = <0>;
4009 thermal-sensors = <&tsens1 12>;
4012 thermal-engine-config {
4018 mdmss2_config0: mdmss2-config0 {
4024 mdmss2_config1: mdmss2-config1 {
4030 reset-mon-cfg {
4038 modem3-thermal {
4039 polling-delay-passive = <0>;
4040 polling-delay = <0>;
4041 thermal-sensors = <&tsens1 13>;
4044 thermal-engine-config {
4050 mdmss3_config0: mdmss3-config0 {
4056 mdmss3_config1: mdmss3-config1 {
4062 reset-mon-cfg {
4070 camera0-thermal {
4071 polling-delay-passive = <0>;
4072 polling-delay = <0>;
4073 thermal-sensors = <&tsens1 14>;
4076 thermal-engine-config {
4082 reset-mon-cfg {
4090 camera1-thermal {
4091 polling-delay-passive = <0>;
4092 polling-delay = <0>;
4093 thermal-sensors = <&tsens1 15>;
4096 thermal-engine-config {
4102 reset-mon-cfg {
4112 compatible = "arm,armv8-timer";
4117 clock-frequency = <19200000>;