Lines Matching +full:0 +full:x80c00000
29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
66 reg = <0x0 0x100>;
71 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x200>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0x0 0x300>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
114 reg = <0x0 0x400>;
130 reg = <0x0 0x500>;
147 reg = <0x0 0x600>;
163 reg = <0x0 0x700>;
215 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
218 arm,psci-suspend-param = <0x40000004>;
225 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
228 arm,psci-suspend-param = <0x40000004>;
237 CLUSTER_SLEEP_0: cluster-sleep-0 {
240 arm,psci-suspend-param = <0x41000044>;
250 arm,psci-suspend-param = <0x4100c344>;
262 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
267 clk_virt: interconnect-0 {
282 reg = <0x0 0xa0000000 0x0 0x0>;
295 #power-domain-cells = <0>;
301 #power-domain-cells = <0>;
307 #power-domain-cells = <0>;
313 #power-domain-cells = <0>;
319 #power-domain-cells = <0>;
325 #power-domain-cells = <0>;
331 #power-domain-cells = <0>;
337 #power-domain-cells = <0>;
343 #power-domain-cells = <0>;
373 reg = <0x0 0x80000000 0x0 0x600000>;
378 reg = <0x0 0x80600000 0x0 0x40000>;
383 reg = <0x0 0x80640000 0x0 0x180000>;
388 reg = <0x0 0x807c0000 0x0 0x40000>;
393 reg = <0x0 0x80800000 0x0 0x60000>;
399 reg = <0x0 0x80860000 0x0 0x20000>;
404 reg = <0x0 0x80880000 0x0 0x20000>;
409 reg = <0x0 0x808a0000 0x0 0x40000>;
414 reg = <0x0 0x808e0000 0x0 0x4000>;
419 reg = <0x0 0x808e4000 0x0 0x10000>;
426 reg = <0x0 0x80900000 0x0 0x200000>;
432 reg = <0x0 0x80b00000 0x0 0x100000>;
437 reg = <0x0 0x80c00000 0x0 0x4600000>;
442 reg = <0x0 0x85700000 0x0 0x700000>;
447 reg = <0x0 0x85e00000 0x0 0x2100000>;
452 reg = <0x0 0x88000000 0x0 0x1900000>;
457 reg = <0x0 0x89900000 0x0 0x2000000>;
462 reg = <0x0 0x8b900000 0x0 0x10000>;
467 reg = <0x0 0x8b910000 0x0 0xa000>;
472 reg = <0x0 0x8b91a000 0x0 0x2000>;
477 reg = <0x0 0x8ba00000 0x0 0x180000>;
483 reg = <0x0 0x8bb80000 0x0 0x60000>;
489 reg = <0x0 0x8bbe0000 0x0 0x20000>;
494 reg = <0x0 0x8bc00000 0x0 0x13200000>;
499 reg = <0x0 0x9ee00000 0x0 0x700000>;
504 reg = <0x0 0x9f500000 0x0 0x800000>;
510 reg = <0x0 0x9fd00000 0x0 0x280000>;
518 reg = <0x0 0xa6e00000 0x0 0x40000>;
523 reg = <0x0 0xa6f00000 0x0 0x100000>;
529 /* Linux kernel image is loaded at 0xa0000000 */
532 reg = <0x0 0xbb000000 0x0 0x5000000>;
537 reg = <0x0 0xc0000000 0x0 0x20000000>;
542 reg = <0x0 0xe0000000 0x0 0x600000>;
547 reg = <0x0 0xe0600000 0x0 0x400000>;
552 reg = <0x0 0xe0a00000 0x0 0x100000>;
557 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
562 reg = <0x0 0xe55f3000 0x0 0x9000>;
567 reg = <0x0 0xe55fc000 0x0 0x4000>;
572 reg = <0x0 0xe5600000 0x0 0x100000>;
577 reg = <0x0 0xe8800000 0x0 0x100000>;
582 reg = <0x0 0xe8900000 0x0 0x1200000>;
587 reg = <0x0 0xe9b00000 0x0 0x500000>;
592 reg = <0x0 0xea000000 0x0 0x3900000>;
597 reg = <0x0 0xed900000 0x0 0x3b00000>;
611 qcom,local-pid = <0>;
635 qcom,local-pid = <0>;
659 qcom,local-pid = <0>;
694 qcom,local-pid = <0>;
709 soc: soc@0 {
712 ranges = <0 0 0 0 0x10 0>;
713 dma-ranges = <0 0 0 0 0x10 0>;
718 reg = <0x0 0x00100000 0x0 0x1f4200>;
735 reg = <0 0x800000 0 0x60000>;
749 dma-channel-mask = <0x7e>;
750 iommus = <&apps_smmu 0x496 0x0>;
756 reg = <0x0 0x008c0000 0x0 0x2000>;
760 iommus = <&apps_smmu 0x483 0x0>;
768 reg = <0x0 0x00880000 0x0 0x4000>;
772 pinctrl-0 = <&qup_i2c15_data_clk>;
775 #size-cells = <0>;
776 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
777 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
778 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
780 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
781 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
788 reg = <0x0 0x00880000 0x0 0x4000>;
793 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
795 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
796 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
798 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
799 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
802 #size-cells = <0>;
808 reg = <0x0 0x00884000 0x0 0x4000>;
812 pinctrl-0 = <&qup_i2c16_data_clk>;
815 #size-cells = <0>;
816 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
817 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
818 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
820 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
828 reg = <0x0 0x00884000 0x0 0x4000>;
833 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
835 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
836 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
842 #size-cells = <0>;
848 reg = <0x0 0x00888000 0x0 0x4000>;
852 pinctrl-0 = <&qup_i2c17_data_clk>;
855 #size-cells = <0>;
856 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
857 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
858 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
868 reg = <0x0 0x00888000 0x0 0x4000>;
873 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
878 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
882 #size-cells = <0>;
888 reg = <0x0 0x0088c000 0x0 0x4000>;
892 pinctrl-0 = <&qup_i2c18_data_clk>;
895 #size-cells = <0>;
896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
900 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
908 reg = <0 0x0088c000 0 0x4000>;
913 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
915 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
916 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
918 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
922 #size-cells = <0>;
928 reg = <0x0 0x00890000 0x0 0x4000>;
932 pinctrl-0 = <&qup_i2c19_data_clk>;
935 #size-cells = <0>;
936 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
937 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
938 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
940 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
948 reg = <0 0x00890000 0 0x4000>;
953 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
955 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
956 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
958 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
962 #size-cells = <0>;
968 reg = <0x0 0x00894000 0x0 0x4000>;
972 pinctrl-0 = <&qup_i2c20_data_clk>;
975 #size-cells = <0>;
976 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
977 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
978 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
980 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
988 reg = <0 0x00894000 0 0x4000>;
992 pinctrl-0 = <&qup_uart20_default>;
995 #size-cells = <0>;
1001 reg = <0 0x00894000 0 0x4000>;
1006 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1008 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1009 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1011 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1015 #size-cells = <0>;
1021 reg = <0x0 0x00898000 0x0 0x4000>;
1025 pinctrl-0 = <&qup_i2c21_data_clk>;
1028 #size-cells = <0>;
1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1030 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1031 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1033 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1041 reg = <0 0x00898000 0 0x4000>;
1046 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1051 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1055 #size-cells = <0>;
1063 reg = <0 0x900000 0 0x60000>;
1077 dma-channel-mask = <0x7e>;
1078 iommus = <&apps_smmu 0x5b6 0x0>;
1084 reg = <0x0 0x009c0000 0x0 0x2000>;
1088 iommus = <&apps_smmu 0x5a3 0x0>;
1089 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1098 reg = <0x0 0x00980000 0x0 0x4000>;
1102 pinctrl-0 = <&qup_i2c0_data_clk>;
1105 #size-cells = <0>;
1106 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1107 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1108 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1110 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1111 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1118 reg = <0x0 0x00980000 0x0 0x4000>;
1123 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1126 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1127 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1128 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1130 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1131 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1134 #size-cells = <0>;
1140 reg = <0x0 0x00984000 0x0 0x4000>;
1144 pinctrl-0 = <&qup_i2c1_data_clk>;
1147 #size-cells = <0>;
1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1149 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1150 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1152 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1160 reg = <0x0 0x00984000 0x0 0x4000>;
1165 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1166 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1167 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1168 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1170 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1174 #size-cells = <0>;
1180 reg = <0x0 0x00988000 0x0 0x4000>;
1184 pinctrl-0 = <&qup_i2c2_data_clk>;
1187 #size-cells = <0>;
1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1189 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1190 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1192 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1200 reg = <0x0 0x00988000 0x0 0x4000>;
1205 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1206 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1207 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1208 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1210 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1214 #size-cells = <0>;
1221 reg = <0x0 0x0098c000 0x0 0x4000>;
1225 pinctrl-0 = <&qup_i2c3_data_clk>;
1228 #size-cells = <0>;
1229 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1230 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1231 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1233 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1241 reg = <0x0 0x0098c000 0x0 0x4000>;
1246 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1247 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1248 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1249 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1251 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1255 #size-cells = <0>;
1261 reg = <0x0 0x00990000 0x0 0x4000>;
1265 pinctrl-0 = <&qup_i2c4_data_clk>;
1268 #size-cells = <0>;
1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1270 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1271 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1273 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1281 reg = <0x0 0x00990000 0x0 0x4000>;
1286 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1290 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1291 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1293 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1297 #size-cells = <0>;
1303 reg = <0x0 0x00994000 0x0 0x4000>;
1307 pinctrl-0 = <&qup_i2c5_data_clk>;
1310 #size-cells = <0>;
1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1312 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1313 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1315 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1323 reg = <0x0 0x00994000 0x0 0x4000>;
1328 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1330 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1331 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1333 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1337 #size-cells = <0>;
1344 reg = <0x0 0x998000 0x0 0x4000>;
1348 pinctrl-0 = <&qup_i2c6_data_clk>;
1351 #size-cells = <0>;
1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1353 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1354 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1356 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1364 reg = <0x0 0x998000 0x0 0x4000>;
1369 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1371 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1372 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1374 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1378 #size-cells = <0>;
1384 reg = <0 0x0099c000 0 0x4000>;
1388 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1391 #size-cells = <0>;
1399 reg = <0 0xa00000 0 0x60000>;
1413 dma-channel-mask = <0x7e>;
1414 iommus = <&apps_smmu 0x56 0x0>;
1420 reg = <0x0 0x00ac0000 0x0 0x6000>;
1424 iommus = <&apps_smmu 0x43 0x0>;
1425 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1434 reg = <0x0 0x00a80000 0x0 0x4000>;
1438 pinctrl-0 = <&qup_i2c8_data_clk>;
1441 #size-cells = <0>;
1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1443 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1444 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1446 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1447 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1454 reg = <0x0 0x00a80000 0x0 0x4000>;
1459 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1460 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1461 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1462 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1464 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1465 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1468 #size-cells = <0>;
1474 reg = <0x0 0x00a84000 0x0 0x4000>;
1478 pinctrl-0 = <&qup_i2c9_data_clk>;
1481 #size-cells = <0>;
1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1483 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1484 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1486 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1494 reg = <0x0 0x00a84000 0x0 0x4000>;
1499 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1501 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1502 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1504 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1508 #size-cells = <0>;
1514 reg = <0x0 0x00a88000 0x0 0x4000>;
1518 pinctrl-0 = <&qup_i2c10_data_clk>;
1521 #size-cells = <0>;
1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1523 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1526 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1534 reg = <0x0 0x00a88000 0x0 0x4000>;
1539 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1541 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1542 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1544 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1548 #size-cells = <0>;
1554 reg = <0x0 0x00a8c000 0x0 0x4000>;
1558 pinctrl-0 = <&qup_i2c11_data_clk>;
1561 #size-cells = <0>;
1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1563 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1564 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1566 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1574 reg = <0x0 0x00a8c000 0x0 0x4000>;
1579 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1581 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1584 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1588 #size-cells = <0>;
1594 reg = <0x0 0x00a90000 0x0 0x4000>;
1598 pinctrl-0 = <&qup_i2c12_data_clk>;
1601 #size-cells = <0>;
1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1603 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1604 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1606 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1614 reg = <0x0 0x00a90000 0x0 0x4000>;
1619 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1624 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1628 #size-cells = <0>;
1634 reg = <0 0x00a94000 0 0x4000>;
1638 pinctrl-0 = <&qup_i2c13_data_clk>;
1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1641 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1642 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1644 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1648 #size-cells = <0>;
1654 reg = <0x0 0x00a94000 0x0 0x4000>;
1659 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1664 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1668 #size-cells = <0>;
1674 reg = <0 0x00a98000 0 0x4000>;
1678 pinctrl-0 = <&qup_i2c14_data_clk>;
1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1684 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1688 #size-cells = <0>;
1694 reg = <0x0 0x00a98000 0x0 0x4000>;
1699 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1704 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1708 #size-cells = <0>;
1715 reg = <0 0x01c00000 0 0x3000>,
1716 <0 0x60000000 0 0xf1d>,
1717 <0 0x60000f20 0 0xa8>,
1718 <0 0x60001000 0 0x1000>,
1719 <0 0x60100000 0 0x100000>;
1722 linux,pci-domain = <0>;
1723 bus-range = <0x00 0xff>;
1729 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1730 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1735 interrupt-map-mask = <0 0 0 0x7>;
1736 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1737 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1738 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1739 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1766 iommus = <&apps_smmu 0x1c00 0x7f>;
1767 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1768 <0x100 &apps_smmu 0x1c01 0x1>;
1783 pinctrl-0 = <&pcie0_default_state>;
1790 reg = <0 0x01c06000 0 0x200>;
1809 reg = <0 0x1c06e00 0 0x200>, /* tx */
1810 <0 0x1c07000 0 0x200>, /* rx */
1811 <0 0x1c06200 0 0x200>, /* pcs */
1812 <0 0x1c06600 0 0x200>; /* pcs_pcie */
1816 #clock-cells = <0>;
1817 #phy-cells = <0>;
1824 reg = <0 0x01c08000 0 0x3000>,
1825 <0 0x40000000 0 0xf1d>,
1826 <0 0x40000f20 0 0xa8>,
1827 <0 0x40001000 0 0x1000>,
1828 <0 0x40100000 0 0x100000>;
1832 bus-range = <0x00 0xff>;
1838 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1839 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1844 interrupt-map-mask = <0 0 0 0x7>;
1845 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1846 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1847 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1848 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1873 iommus = <&apps_smmu 0x1c80 0x7f>;
1874 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1875 <0x100 &apps_smmu 0x1c81 0x1>;
1890 pinctrl-0 = <&pcie1_default_state>;
1897 reg = <0 0x01c0f000 0 0x200>;
1916 reg = <0 0x1c0e000 0 0x200>, /* tx */
1917 <0 0x1c0e200 0 0x300>, /* rx */
1918 <0 0x1c0f200 0 0x200>, /* pcs */
1919 <0 0x1c0e800 0 0x200>, /* tx */
1920 <0 0x1c0ea00 0 0x300>, /* rx */
1921 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */
1925 #clock-cells = <0>;
1926 #phy-cells = <0>;
1933 reg = <0 0x01500000 0 0x1c000>;
1940 reg = <0 0x01680000 0 0x1e200>;
1947 reg = <0 0x016c0000 0 0xe280>;
1954 reg = <0 0x016e0000 0 0x1c080>;
1963 reg = <0 0x01700000 0 0x31080>;
1974 reg = <0 0x01740000 0 0x1f080>;
1981 reg = <0x0 0x01f40000 0x0 0x40000>;
1988 reg = <0 0x088e3000 0 0x400>;
1990 #phy-cells = <0>;
2000 reg = <0 0x088e9000 0 0x200>,
2001 <0 0x088e8000 0 0x20>;
2017 reg = <0 0x088e9200 0 0x200>,
2018 <0 0x088e9400 0 0x200>,
2019 <0 0x088e9c00 0 0x400>,
2020 <0 0x088e9600 0 0x200>,
2021 <0 0x088e9800 0 0x200>,
2022 <0 0x088e9a00 0 0x100>;
2023 #phy-cells = <0>;
2024 #clock-cells = <0>;
2033 reg = <0 0x02400000 0 0x4000>;
2036 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2054 qcom,smem-states = <&smp2p_slpi_out 0>;
2074 #size-cells = <0>;
2079 iommus = <&apps_smmu 0x0541 0x0>;
2085 iommus = <&apps_smmu 0x0542 0x0>;
2091 iommus = <&apps_smmu 0x0543 0x0>;
2100 reg = <0 0x030000000 0 0x100>;
2103 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2121 qcom,smem-states = <&smp2p_adsp_out 0>;
2141 #size-cells = <0>;
2146 iommus = <&apps_smmu 0x1803 0x0>;
2152 iommus = <&apps_smmu 0x1804 0x0>;
2158 iommus = <&apps_smmu 0x1805 0x0>;
2166 reg = <0 0x032300000 0 0x1400000>;
2169 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2187 qcom,smem-states = <&smp2p_cdsp_out 0>;
2207 #size-cells = <0>;
2212 iommus = <&apps_smmu 0x2161 0x0400>,
2213 <&apps_smmu 0x1021 0x1420>;
2219 iommus = <&apps_smmu 0x2162 0x0400>,
2220 <&apps_smmu 0x1022 0x1420>;
2226 iommus = <&apps_smmu 0x2163 0x0400>,
2227 <&apps_smmu 0x1023 0x1420>;
2233 iommus = <&apps_smmu 0x2164 0x0400>,
2234 <&apps_smmu 0x1024 0x1420>;
2240 iommus = <&apps_smmu 0x2165 0x0400>,
2241 <&apps_smmu 0x1025 0x1420>;
2247 iommus = <&apps_smmu 0x2166 0x0400>,
2248 <&apps_smmu 0x1026 0x1420>;
2254 iommus = <&apps_smmu 0x2167 0x0400>,
2255 <&apps_smmu 0x1027 0x1420>;
2261 iommus = <&apps_smmu 0x2168 0x0400>,
2262 <&apps_smmu 0x1028 0x1420>;
2272 reg = <0x0 0x04080000 0x0 0x4040>;
2275 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2286 power-domains = <&rpmhpd 0>,
2294 qcom,smem-states = <&smp2p_modem_out 0>;
2312 reg = <0 0x0ade0000 0 0x20000>;
2327 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2328 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
2337 reg = <0 0x0c263000 0 0x1000>, /* TM */
2338 <0 0x0c222000 0 0x1000>; /* SROT */
2348 reg = <0 0x0c265000 0 0x1000>, /* TM */
2349 <0 0x0c223000 0 0x1000>; /* SROT */
2359 reg = <0 0x0c300000 0 0x400>;
2364 #clock-cells = <0>;
2369 reg = <0 0x0ed18000 0 0x1000>;
2378 reg = <0 0x0f100000 0 0x300000>;
2384 gpio-ranges = <&tlmm 0 0 211>;
2805 reg = <0 0x15000000 0 0x100000>;
2912 redistributor-stride = <0x0 0x40000>;
2913 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
2914 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
2922 reg = <0x0 0x17140000 0x0 0x20000>;
2932 ranges = <0 0 0 0x20000000>;
2933 reg = <0x0 0x17420000 0x0 0x1000>;
2937 frame-number = <0>;
2940 reg = <0x17421000 0x1000>,
2941 <0x17422000 0x1000>;
2947 reg = <0x17423000 0x1000>;
2954 reg = <0x17425000 0x1000>;
2961 reg = <0x17427000 0x1000>;
2968 reg = <0x17429000 0x1000>;
2975 reg = <0x1742b000 0x1000>;
2982 reg = <0x1742d000 0x1000>;
2990 reg = <0x0 0x17a00000 0x0 0x10000>,
2991 <0x0 0x17a10000 0x0 0x10000>,
2992 <0x0 0x17a20000 0x0 0x10000>,
2993 <0x0 0x17a30000 0x0 0x10000>;
2994 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
2998 qcom,tcs-offset = <0xd00>;
3001 <WAKE_TCS 2>, <CONTROL_TCS 0>;
3067 reg = <0 0x17d91000 0 0x1000>,
3068 <0 0x17d92000 0 0x1000>,
3069 <0 0x17d93000 0 0x1000>;
3076 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3082 reg = <0 0x19100000 0 0xbb800>;
3089 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
3097 reg = <0 0x01d84000 0 0x3000>,
3098 <0 0x01d88000 0 0x8000>;
3110 iommus = <&apps_smmu 0xe0 0x0>;
3112 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
3113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
3137 <0 0>,
3138 <0 0>,
3141 <0 0>,
3142 <0 0>,
3143 <0 0>,
3150 reg = <0 0x01d87000 0 0x1c4>;
3159 resets = <&ufs_mem_hc 0>;
3164 reg = <0 0x01d87400 0 0x108>,
3165 <0 0x01d87600 0 0x1e0>,
3166 <0 0x01d87c00 0 0x1dc>,
3167 <0 0x01d87800 0 0x108>,
3168 <0 0x01d87a00 0 0x1e0>;
3169 #phy-cells = <0>;
3175 reg = <0 0x08804000 0 0x1000>;
3186 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3189 iommus = <&apps_smmu 0x4a0 0x0>;
3214 reg = <0 0x0a6f8800 0 0x400>;
3252 reg = <0 0x0a600000 0 0xcd00>;
3254 iommus = <&apps_smmu 0x0 0x0>;
3264 reg = <0 0x320c0000 0 0x10000>;
3271 reg = <0 0x3c40000 0 0x17200>;
3279 polling-delay-passive = <0>;
3280 polling-delay = <0>;
3281 thermal-sensors = <&tsens0 0>;
3299 polling-delay-passive = <0>;
3300 polling-delay = <0>;
3319 polling-delay-passive = <0>;
3320 polling-delay = <0>;
3339 polling-delay-passive = <0>;
3340 polling-delay = <0>;
3359 polling-delay-passive = <0>;
3360 polling-delay = <0>;
3379 polling-delay-passive = <0>;
3380 polling-delay = <0>;
3405 polling-delay-passive = <0>;
3406 polling-delay = <0>;
3431 polling-delay-passive = <0>;
3432 polling-delay = <0>;
3457 polling-delay-passive = <0>;
3458 polling-delay = <0>;
3483 polling-delay-passive = <0>;
3484 polling-delay = <0>;
3509 polling-delay-passive = <0>;
3510 polling-delay = <0>;
3535 polling-delay-passive = <0>;
3536 polling-delay = <0>;
3561 polling-delay-passive = <0>;
3562 polling-delay = <0>;
3587 polling-delay-passive = <0>;
3588 polling-delay = <0>;
3614 polling-delay = <0>;
3646 polling-delay = <0>;
3677 polling-delay-passive = <0>;
3678 polling-delay = <0>;
3679 thermal-sensors = <&tsens1 0>;
3697 polling-delay-passive = <0>;
3698 polling-delay = <0>;
3723 polling-delay-passive = <0>;
3724 polling-delay = <0>;
3749 polling-delay-passive = <0>;
3750 polling-delay = <0>;
3775 polling-delay-passive = <0>;
3776 polling-delay = <0>;
3802 polling-delay = <0>;
3834 polling-delay = <0>;
3866 polling-delay = <0>;
3897 polling-delay-passive = <0>;
3898 polling-delay = <0>;
3918 polling-delay = <0>;
3943 polling-delay-passive = <0>;
3944 polling-delay = <0>;
3975 polling-delay-passive = <0>;
3976 polling-delay = <0>;
4007 polling-delay-passive = <0>;
4008 polling-delay = <0>;
4039 polling-delay-passive = <0>;
4040 polling-delay = <0>;
4071 polling-delay-passive = <0>;
4072 polling-delay = <0>;
4091 polling-delay-passive = <0>;
4092 polling-delay = <0>;