Lines Matching +full:qcom +full:- +full:ipcc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sm8350.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/interconnect/qcom,sm8350.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <38400000>;
32 clock-output-names = "xo_board";
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 clock-frequency = <32000>;
38 #clock-cells = <0>;
41 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
42 compatible = "fixed-clock";
43 clock-frequency = <1000>;
44 #clock-cells = <0>;
47 ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
48 compatible = "fixed-clock";
49 clock-frequency = <1000>;
50 #clock-cells = <0>;
53 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
54 compatible = "fixed-clock";
55 clock-frequency = <1000>;
56 #clock-cells = <0>;
61 #address-cells = <2>;
62 #size-cells = <0>;
66 compatible = "qcom,kryo685";
68 enable-method = "psci";
69 next-level-cache = <&L2_0>;
70 qcom,freq-domain = <&cpufreq_hw 0>;
71 power-domains = <&CPU_PD0>;
72 power-domain-names = "psci";
73 #cooling-cells = <2>;
74 L2_0: l2-cache {
76 next-level-cache = <&L3_0>;
77 L3_0: l3-cache {
85 compatible = "qcom,kryo685";
87 enable-method = "psci";
88 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
90 power-domains = <&CPU_PD1>;
91 power-domain-names = "psci";
92 #cooling-cells = <2>;
93 L2_100: l2-cache {
95 next-level-cache = <&L3_0>;
101 compatible = "qcom,kryo685";
103 enable-method = "psci";
104 next-level-cache = <&L2_200>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 power-domains = <&CPU_PD2>;
107 power-domain-names = "psci";
108 #cooling-cells = <2>;
109 L2_200: l2-cache {
111 next-level-cache = <&L3_0>;
117 compatible = "qcom,kryo685";
119 enable-method = "psci";
120 next-level-cache = <&L2_300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 power-domains = <&CPU_PD3>;
123 power-domain-names = "psci";
124 #cooling-cells = <2>;
125 L2_300: l2-cache {
127 next-level-cache = <&L3_0>;
133 compatible = "qcom,kryo685";
135 enable-method = "psci";
136 next-level-cache = <&L2_400>;
137 qcom,freq-domain = <&cpufreq_hw 1>;
138 power-domains = <&CPU_PD4>;
139 power-domain-names = "psci";
140 #cooling-cells = <2>;
141 L2_400: l2-cache {
143 next-level-cache = <&L3_0>;
149 compatible = "qcom,kryo685";
151 enable-method = "psci";
152 next-level-cache = <&L2_500>;
153 qcom,freq-domain = <&cpufreq_hw 1>;
154 power-domains = <&CPU_PD5>;
155 power-domain-names = "psci";
156 #cooling-cells = <2>;
157 L2_500: l2-cache {
159 next-level-cache = <&L3_0>;
166 compatible = "qcom,kryo685";
168 enable-method = "psci";
169 next-level-cache = <&L2_600>;
170 qcom,freq-domain = <&cpufreq_hw 1>;
171 power-domains = <&CPU_PD6>;
172 power-domain-names = "psci";
173 #cooling-cells = <2>;
174 L2_600: l2-cache {
176 next-level-cache = <&L3_0>;
182 compatible = "qcom,kryo685";
184 enable-method = "psci";
185 next-level-cache = <&L2_700>;
186 qcom,freq-domain = <&cpufreq_hw 2>;
187 power-domains = <&CPU_PD7>;
188 power-domain-names = "psci";
189 #cooling-cells = <2>;
190 L2_700: l2-cache {
192 next-level-cache = <&L3_0>;
196 cpu-map {
232 idle-states {
233 entry-method = "psci";
235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
236 compatible = "arm,idle-state";
237 idle-state-name = "silver-rail-power-collapse";
238 arm,psci-suspend-param = <0x40000004>;
239 entry-latency-us = <355>;
240 exit-latency-us = <909>;
241 min-residency-us = <3934>;
242 local-timer-stop;
245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
246 compatible = "arm,idle-state";
247 idle-state-name = "gold-rail-power-collapse";
248 arm,psci-suspend-param = <0x40000004>;
249 entry-latency-us = <241>;
250 exit-latency-us = <1461>;
251 min-residency-us = <4488>;
252 local-timer-stop;
256 domain-idle-states {
257 CLUSTER_SLEEP_0: cluster-sleep-0 {
258 compatible = "domain-idle-state";
259 idle-state-name = "cluster-power-collapse";
260 arm,psci-suspend-param = <0x4100c344>;
261 entry-latency-us = <3263>;
262 exit-latency-us = <6562>;
263 min-residency-us = <9987>;
264 local-timer-stop;
271 compatible = "qcom,scm-sm8350", "qcom,scm";
272 #reset-cells = <1>;
283 compatible = "arm,armv8-pmuv3";
288 compatible = "arm,psci-1.0";
292 #power-domain-cells = <0>;
293 power-domains = <&CLUSTER_PD>;
294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
298 #power-domain-cells = <0>;
299 power-domains = <&CLUSTER_PD>;
300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
304 #power-domain-cells = <0>;
305 power-domains = <&CLUSTER_PD>;
306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
310 #power-domain-cells = <0>;
311 power-domains = <&CLUSTER_PD>;
312 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
316 #power-domain-cells = <0>;
317 power-domains = <&CLUSTER_PD>;
318 domain-idle-states = <&BIG_CPU_SLEEP_0>;
322 #power-domain-cells = <0>;
323 power-domains = <&CLUSTER_PD>;
324 domain-idle-states = <&BIG_CPU_SLEEP_0>;
328 #power-domain-cells = <0>;
329 power-domains = <&CLUSTER_PD>;
330 domain-idle-states = <&BIG_CPU_SLEEP_0>;
334 #power-domain-cells = <0>;
335 power-domains = <&CLUSTER_PD>;
336 domain-idle-states = <&BIG_CPU_SLEEP_0>;
339 CLUSTER_PD: cpu-cluster0 {
340 #power-domain-cells = <0>;
341 domain-idle-states = <&CLUSTER_SLEEP_0>;
345 qup_opp_table_100mhz: opp-table-qup100mhz {
346 compatible = "operating-points-v2";
348 opp-50000000 {
349 opp-hz = /bits/ 64 <50000000>;
350 required-opps = <&rpmhpd_opp_min_svs>;
353 opp-75000000 {
354 opp-hz = /bits/ 64 <75000000>;
355 required-opps = <&rpmhpd_opp_low_svs>;
358 opp-100000000 {
359 opp-hz = /bits/ 64 <100000000>;
360 required-opps = <&rpmhpd_opp_svs>;
364 qup_opp_table_120mhz: opp-table-qup120mhz {
365 compatible = "operating-points-v2";
367 opp-50000000 {
368 opp-hz = /bits/ 64 <50000000>;
369 required-opps = <&rpmhpd_opp_min_svs>;
372 opp-75000000 {
373 opp-hz = /bits/ 64 <75000000>;
374 required-opps = <&rpmhpd_opp_low_svs>;
377 opp-120000000 {
378 opp-hz = /bits/ 64 <120000000>;
379 required-opps = <&rpmhpd_opp_svs>;
383 reserved_memory: reserved-memory {
384 #address-cells = <2>;
385 #size-cells = <2>;
390 no-map;
394 no-map;
399 compatible = "qcom,cmd-db";
401 no-map;
406 no-map;
411 no-map;
416 no-map;
421 no-map;
426 no-map;
431 no-map;
436 no-map;
441 no-map;
446 no-map;
451 no-map;
456 no-map;
461 no-map;
466 no-map;
471 no-map;
476 no-map;
480 compatible = "qcom,rmtfs-mem";
482 no-map;
484 qcom,client-id = <1>;
485 qcom,vmid = <15>;
490 no-map;
495 no-map;
500 no-map;
505 no-map;
510 no-map;
515 no-map;
519 smem: qcom,smem {
520 compatible = "qcom,smem";
521 memory-region = <&smem_mem>;
525 smp2p-adsp {
526 compatible = "qcom,smp2p";
527 qcom,smem = <443>, <429>;
528 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
531 mboxes = <&ipcc IPCC_CLIENT_LPASS
534 qcom,local-pid = <0>;
535 qcom,remote-pid = <2>;
537 smp2p_adsp_out: master-kernel {
538 qcom,entry-name = "master-kernel";
539 #qcom,smem-state-cells = <1>;
542 smp2p_adsp_in: slave-kernel {
543 qcom,entry-name = "slave-kernel";
544 interrupt-controller;
545 #interrupt-cells = <2>;
549 smp2p-cdsp {
550 compatible = "qcom,smp2p";
551 qcom,smem = <94>, <432>;
552 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
555 mboxes = <&ipcc IPCC_CLIENT_CDSP
558 qcom,local-pid = <0>;
559 qcom,remote-pid = <5>;
561 smp2p_cdsp_out: master-kernel {
562 qcom,entry-name = "master-kernel";
563 #qcom,smem-state-cells = <1>;
566 smp2p_cdsp_in: slave-kernel {
567 qcom,entry-name = "slave-kernel";
568 interrupt-controller;
569 #interrupt-cells = <2>;
573 smp2p-modem {
574 compatible = "qcom,smp2p";
575 qcom,smem = <435>, <428>;
576 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
579 mboxes = <&ipcc IPCC_CLIENT_MPSS
582 qcom,local-pid = <0>;
583 qcom,remote-pid = <1>;
585 smp2p_modem_out: master-kernel {
586 qcom,entry-name = "master-kernel";
587 #qcom,smem-state-cells = <1>;
590 smp2p_modem_in: slave-kernel {
591 qcom,entry-name = "slave-kernel";
592 interrupt-controller;
593 #interrupt-cells = <2>;
596 ipa_smp2p_out: ipa-ap-to-modem {
597 qcom,entry-name = "ipa";
598 #qcom,smem-state-cells = <1>;
601 ipa_smp2p_in: ipa-modem-to-ap {
602 qcom,entry-name = "ipa";
603 interrupt-controller;
604 #interrupt-cells = <2>;
608 smp2p-slpi {
609 compatible = "qcom,smp2p";
610 qcom,smem = <481>, <430>;
611 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
614 mboxes = <&ipcc IPCC_CLIENT_SLPI
617 qcom,local-pid = <0>;
618 qcom,remote-pid = <3>;
620 smp2p_slpi_out: master-kernel {
621 qcom,entry-name = "master-kernel";
622 #qcom,smem-state-cells = <1>;
625 smp2p_slpi_in: slave-kernel {
626 qcom,entry-name = "slave-kernel";
627 interrupt-controller;
628 #interrupt-cells = <2>;
633 #address-cells = <2>;
634 #size-cells = <2>;
636 dma-ranges = <0 0 0 0 0x10 0>;
637 compatible = "simple-bus";
639 gcc: clock-controller@100000 {
640 compatible = "qcom,gcc-sm8350";
642 #clock-cells = <1>;
643 #reset-cells = <1>;
644 #power-domain-cells = <1>;
645 clock-names = "bi_tcxo",
671 ipcc: mailbox@408000 { label
672 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
675 interrupt-controller;
676 #interrupt-cells = <3>;
677 #mbox-cells = <2>;
680 gpi_dma2: dma-controller@800000 {
681 compatible = "qcom,sm8350-gpi-dma";
695 dma-channels = <12>;
696 dma-channel-mask = <0xff>;
698 #dma-cells = <3>;
703 compatible = "qcom,geni-se-qup";
705 clock-names = "m-ahb", "s-ahb";
709 #address-cells = <2>;
710 #size-cells = <2>;
715 compatible = "qcom,geni-i2c";
717 clock-names = "se";
719 pinctrl-names = "default";
720 pinctrl-0 = <&qup_i2c14_default>;
724 dma-names = "tx", "rx";
725 #address-cells = <1>;
726 #size-cells = <0>;
731 compatible = "qcom,geni-spi";
733 clock-names = "se";
736 power-domains = <&rpmhpd SM8350_CX>;
737 operating-points-v2 = <&qup_opp_table_120mhz>;
740 dma-names = "tx", "rx";
741 #address-cells = <1>;
742 #size-cells = <0>;
747 compatible = "qcom,geni-i2c";
749 clock-names = "se";
751 pinctrl-names = "default";
752 pinctrl-0 = <&qup_i2c15_default>;
756 dma-names = "tx", "rx";
757 #address-cells = <1>;
758 #size-cells = <0>;
763 compatible = "qcom,geni-spi";
765 clock-names = "se";
768 power-domains = <&rpmhpd SM8350_CX>;
769 operating-points-v2 = <&qup_opp_table_120mhz>;
772 dma-names = "tx", "rx";
773 #address-cells = <1>;
774 #size-cells = <0>;
779 compatible = "qcom,geni-i2c";
781 clock-names = "se";
783 pinctrl-names = "default";
784 pinctrl-0 = <&qup_i2c16_default>;
788 dma-names = "tx", "rx";
789 #address-cells = <1>;
790 #size-cells = <0>;
795 compatible = "qcom,geni-spi";
797 clock-names = "se";
800 power-domains = <&rpmhpd SM8350_CX>;
801 operating-points-v2 = <&qup_opp_table_100mhz>;
804 dma-names = "tx", "rx";
805 #address-cells = <1>;
806 #size-cells = <0>;
811 compatible = "qcom,geni-i2c";
813 clock-names = "se";
815 pinctrl-names = "default";
816 pinctrl-0 = <&qup_i2c17_default>;
820 dma-names = "tx", "rx";
821 #address-cells = <1>;
822 #size-cells = <0>;
827 compatible = "qcom,geni-spi";
829 clock-names = "se";
832 power-domains = <&rpmhpd SM8350_CX>;
833 operating-points-v2 = <&qup_opp_table_100mhz>;
836 dma-names = "tx", "rx";
837 #address-cells = <1>;
838 #size-cells = <0>;
842 /* QUP no. 18 seems to be strictly SPI/UART-only */
845 compatible = "qcom,geni-spi";
847 clock-names = "se";
850 power-domains = <&rpmhpd SM8350_CX>;
851 operating-points-v2 = <&qup_opp_table_100mhz>;
854 dma-names = "tx", "rx";
855 #address-cells = <1>;
856 #size-cells = <0>;
861 compatible = "qcom,geni-uart";
863 clock-names = "se";
865 pinctrl-names = "default";
866 pinctrl-0 = <&qup_uart18_default>;
868 power-domains = <&rpmhpd SM8350_CX>;
869 operating-points-v2 = <&qup_opp_table_100mhz>;
874 compatible = "qcom,geni-i2c";
876 clock-names = "se";
878 pinctrl-names = "default";
879 pinctrl-0 = <&qup_i2c19_default>;
883 dma-names = "tx", "rx";
884 #address-cells = <1>;
885 #size-cells = <0>;
890 compatible = "qcom,geni-spi";
892 clock-names = "se";
895 power-domains = <&rpmhpd SM8350_CX>;
896 operating-points-v2 = <&qup_opp_table_100mhz>;
899 dma-names = "tx", "rx";
900 #address-cells = <1>;
901 #size-cells = <0>;
906 gpi_dma0: dma-controller@900000 {
907 compatible = "qcom,sm8350-gpi-dma";
921 dma-channels = <12>;
922 dma-channel-mask = <0x7e>;
924 #dma-cells = <3>;
929 compatible = "qcom,geni-se-qup";
931 clock-names = "m-ahb", "s-ahb";
935 #address-cells = <2>;
936 #size-cells = <2>;
941 compatible = "qcom,geni-i2c";
943 clock-names = "se";
945 pinctrl-names = "default";
946 pinctrl-0 = <&qup_i2c0_default>;
950 dma-names = "tx", "rx";
951 #address-cells = <1>;
952 #size-cells = <0>;
957 compatible = "qcom,geni-spi";
959 clock-names = "se";
962 power-domains = <&rpmhpd SM8350_CX>;
963 operating-points-v2 = <&qup_opp_table_100mhz>;
966 dma-names = "tx", "rx";
967 #address-cells = <1>;
968 #size-cells = <0>;
973 compatible = "qcom,geni-i2c";
975 clock-names = "se";
977 pinctrl-names = "default";
978 pinctrl-0 = <&qup_i2c1_default>;
982 dma-names = "tx", "rx";
983 #address-cells = <1>;
984 #size-cells = <0>;
989 compatible = "qcom,geni-spi";
991 clock-names = "se";
994 power-domains = <&rpmhpd SM8350_CX>;
995 operating-points-v2 = <&qup_opp_table_100mhz>;
998 dma-names = "tx", "rx";
999 #address-cells = <1>;
1000 #size-cells = <0>;
1005 compatible = "qcom,geni-i2c";
1007 clock-names = "se";
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&qup_i2c2_default>;
1014 dma-names = "tx", "rx";
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1021 compatible = "qcom,geni-spi";
1023 clock-names = "se";
1026 power-domains = <&rpmhpd SM8350_CX>;
1027 operating-points-v2 = <&qup_opp_table_100mhz>;
1030 dma-names = "tx", "rx";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1037 compatible = "qcom,geni-debug-uart";
1039 clock-names = "se";
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&qup_uart3_default_state>;
1044 power-domains = <&rpmhpd SM8350_CX>;
1045 operating-points-v2 = <&qup_opp_table_100mhz>;
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1051 /* QUP no. 3 seems to be strictly SPI-only */
1054 compatible = "qcom,geni-spi";
1056 clock-names = "se";
1059 power-domains = <&rpmhpd SM8350_CX>;
1060 operating-points-v2 = <&qup_opp_table_100mhz>;
1063 dma-names = "tx", "rx";
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1070 compatible = "qcom,geni-i2c";
1072 clock-names = "se";
1074 pinctrl-names = "default";
1075 pinctrl-0 = <&qup_i2c4_default>;
1079 dma-names = "tx", "rx";
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1086 compatible = "qcom,geni-spi";
1088 clock-names = "se";
1091 power-domains = <&rpmhpd SM8350_CX>;
1092 operating-points-v2 = <&qup_opp_table_100mhz>;
1095 dma-names = "tx", "rx";
1096 #address-cells = <1>;
1097 #size-cells = <0>;
1102 compatible = "qcom,geni-i2c";
1104 clock-names = "se";
1106 pinctrl-names = "default";
1107 pinctrl-0 = <&qup_i2c5_default>;
1111 dma-names = "tx", "rx";
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1118 compatible = "qcom,geni-spi";
1120 clock-names = "se";
1123 power-domains = <&rpmhpd SM8350_CX>;
1124 operating-points-v2 = <&qup_opp_table_100mhz>;
1127 dma-names = "tx", "rx";
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1134 compatible = "qcom,geni-i2c";
1136 clock-names = "se";
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&qup_i2c6_default>;
1143 dma-names = "tx", "rx";
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1150 compatible = "qcom,geni-spi";
1152 clock-names = "se";
1155 power-domains = <&rpmhpd SM8350_CX>;
1156 operating-points-v2 = <&qup_opp_table_100mhz>;
1159 dma-names = "tx", "rx";
1160 #address-cells = <1>;
1161 #size-cells = <0>;
1166 compatible = "qcom,geni-uart";
1168 clock-names = "se";
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&qup_uart6_default>;
1173 power-domains = <&rpmhpd SM8350_CX>;
1174 operating-points-v2 = <&qup_opp_table_100mhz>;
1179 compatible = "qcom,geni-i2c";
1181 clock-names = "se";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&qup_i2c7_default>;
1188 dma-names = "tx", "rx";
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1195 compatible = "qcom,geni-spi";
1197 clock-names = "se";
1200 power-domains = <&rpmhpd SM8350_CX>;
1201 operating-points-v2 = <&qup_opp_table_100mhz>;
1204 dma-names = "tx", "rx";
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1211 gpi_dma1: dma-controller@a00000 {
1212 compatible = "qcom,sm8350-gpi-dma";
1226 dma-channels = <12>;
1227 dma-channel-mask = <0xff>;
1229 #dma-cells = <3>;
1234 compatible = "qcom,geni-se-qup";
1236 clock-names = "m-ahb", "s-ahb";
1240 #address-cells = <2>;
1241 #size-cells = <2>;
1246 compatible = "qcom,geni-i2c";
1248 clock-names = "se";
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&qup_i2c8_default>;
1255 dma-names = "tx", "rx";
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1262 compatible = "qcom,geni-spi";
1264 clock-names = "se";
1267 power-domains = <&rpmhpd SM8350_CX>;
1268 operating-points-v2 = <&qup_opp_table_120mhz>;
1271 dma-names = "tx", "rx";
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1278 compatible = "qcom,geni-i2c";
1280 clock-names = "se";
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&qup_i2c9_default>;
1287 dma-names = "tx", "rx";
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1294 compatible = "qcom,geni-spi";
1296 clock-names = "se";
1299 power-domains = <&rpmhpd SM8350_CX>;
1300 operating-points-v2 = <&qup_opp_table_100mhz>;
1303 dma-names = "tx", "rx";
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1310 compatible = "qcom,geni-i2c";
1312 clock-names = "se";
1314 pinctrl-names = "default";
1315 pinctrl-0 = <&qup_i2c10_default>;
1319 dma-names = "tx", "rx";
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1326 compatible = "qcom,geni-spi";
1328 clock-names = "se";
1331 power-domains = <&rpmhpd SM8350_CX>;
1332 operating-points-v2 = <&qup_opp_table_100mhz>;
1335 dma-names = "tx", "rx";
1336 #address-cells = <1>;
1337 #size-cells = <0>;
1342 compatible = "qcom,geni-i2c";
1344 clock-names = "se";
1346 pinctrl-names = "default";
1347 pinctrl-0 = <&qup_i2c11_default>;
1351 dma-names = "tx", "rx";
1352 #address-cells = <1>;
1353 #size-cells = <0>;
1358 compatible = "qcom,geni-spi";
1360 clock-names = "se";
1363 power-domains = <&rpmhpd SM8350_CX>;
1364 operating-points-v2 = <&qup_opp_table_100mhz>;
1367 dma-names = "tx", "rx";
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1374 compatible = "qcom,geni-i2c";
1376 clock-names = "se";
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&qup_i2c12_default>;
1383 dma-names = "tx", "rx";
1384 #address-cells = <1>;
1385 #size-cells = <0>;
1390 compatible = "qcom,geni-spi";
1392 clock-names = "se";
1395 power-domains = <&rpmhpd SM8350_CX>;
1396 operating-points-v2 = <&qup_opp_table_100mhz>;
1399 dma-names = "tx", "rx";
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1406 compatible = "qcom,geni-i2c";
1408 clock-names = "se";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_i2c13_default>;
1415 dma-names = "tx", "rx";
1416 #address-cells = <1>;
1417 #size-cells = <0>;
1422 compatible = "qcom,geni-spi";
1424 clock-names = "se";
1427 power-domains = <&rpmhpd SM8350_CX>;
1428 operating-points-v2 = <&qup_opp_table_100mhz>;
1431 dma-names = "tx", "rx";
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1439 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
1441 #iommu-cells = <2>;
1442 #global-interrupts = <2>;
1544 compatible = "qcom,sm8350-config-noc";
1546 #interconnect-cells = <1>;
1547 qcom,bcm-voters = <&apps_bcm_voter>;
1551 compatible = "qcom,sm8350-mc-virt";
1553 #interconnect-cells = <1>;
1554 qcom,bcm-voters = <&apps_bcm_voter>;
1558 compatible = "qcom,sm8350-system-noc";
1560 #interconnect-cells = <1>;
1561 qcom,bcm-voters = <&apps_bcm_voter>;
1565 compatible = "qcom,sm8350-aggre1-noc";
1567 #interconnect-cells = <1>;
1568 qcom,bcm-voters = <&apps_bcm_voter>;
1572 compatible = "qcom,sm8350-aggre2-noc";
1574 #interconnect-cells = <1>;
1575 qcom,bcm-voters = <&apps_bcm_voter>;
1579 compatible = "qcom,sm8350-mmss-noc";
1581 #interconnect-cells = <1>;
1582 qcom,bcm-voters = <&apps_bcm_voter>;
1586 compatible = "qcom,sm8350-lpass-ag-noc";
1588 #interconnect-cells = <1>;
1589 qcom,bcm-voters = <&apps_bcm_voter>;
1593 compatible = "qcom,sm8350-compute-noc";
1595 #interconnect-cells = <1>;
1596 qcom,bcm-voters = <&apps_bcm_voter>;
1600 compatible = "qcom,sm8350-ipa";
1607 reg-names = "ipa-reg",
1608 "ipa-shared",
1611 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1615 interrupt-names = "ipa",
1617 "ipa-clock-query",
1618 "ipa-setup-ready";
1621 clock-names = "core";
1625 interconnect-names = "memory",
1628 qcom,qmp = <&aoss_qmp>;
1630 qcom,smem-states = <&ipa_smp2p_out 0>,
1632 qcom,smem-state-names = "ipa-clock-enabled-valid",
1633 "ipa-clock-enabled";
1639 compatible = "qcom,tcsr-mutex";
1641 #hwlock-cells = <1>;
1645 compatible = "qcom,sm8350-mpss-pas";
1648 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1654 interrupt-names = "wdog", "fatal", "ready", "handover",
1655 "stop-ack", "shutdown-ack";
1658 clock-names = "xo";
1660 power-domains = <&rpmhpd SM8350_CX>,
1662 power-domain-names = "cx", "mss";
1666 memory-region = <&pil_modem_mem>;
1668 qcom,qmp = <&aoss_qmp>;
1670 qcom,smem-states = <&smp2p_modem_out 0>;
1671 qcom,smem-state-names = "stop";
1675 glink-edge {
1676 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1679 mboxes = <&ipcc IPCC_CLIENT_MPSS
1682 qcom,remote-pid = <1>;
1686 pdc: interrupt-controller@b220000 {
1687 compatible = "qcom,sm8350-pdc", "qcom,pdc";
1689 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
1693 #interrupt-cells = <2>;
1694 interrupt-parent = <&intc>;
1695 interrupt-controller;
1698 tsens0: thermal-sensor@c263000 {
1699 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1702 #qcom,sensors = <15>;
1703 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1705 interrupt-names = "uplow", "critical";
1706 #thermal-sensor-cells = <1>;
1709 tsens1: thermal-sensor@c265000 {
1710 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1713 #qcom,sensors = <14>;
1714 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1716 interrupt-names = "uplow", "critical";
1717 #thermal-sensor-cells = <1>;
1720 aoss_qmp: power-controller@c300000 {
1721 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
1723 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1725 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1727 #clock-cells = <0>;
1731 compatible = "qcom,rpmh-stats";
1736 compatible = "qcom,spmi-pmic-arb";
1742 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1743 interrupt-names = "periph_irq";
1744 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1745 qcom,ee = <0>;
1746 qcom,channel = <0>;
1747 #address-cells = <2>;
1748 #size-cells = <0>;
1749 interrupt-controller;
1750 #interrupt-cells = <4>;
1754 compatible = "qcom,sm8350-tlmm";
1757 gpio-controller;
1758 #gpio-cells = <2>;
1759 interrupt-controller;
1760 #interrupt-cells = <2>;
1761 gpio-ranges = <&tlmm 0 0 204>;
1762 wakeup-parent = <&pdc>;
1764 qup_uart3_default_state: qup-uart3-default-state {
1765 rx-pins {
1769 tx-pins {
1775 qup_uart6_default: qup-uart6-default-state {
1778 drive-strength = <2>;
1779 bias-disable;
1782 qup_uart18_default: qup-uart18-default-state {
1785 drive-strength = <2>;
1786 bias-disable;
1789 qup_i2c0_default: qup-i2c0-default-state {
1792 drive-strength = <2>;
1793 bias-pull-up;
1796 qup_i2c1_default: qup-i2c1-default-state {
1799 drive-strength = <2>;
1800 bias-pull-up;
1803 qup_i2c2_default: qup-i2c2-default-state {
1806 drive-strength = <2>;
1807 bias-pull-up;
1810 qup_i2c4_default: qup-i2c4-default-state {
1813 drive-strength = <2>;
1814 bias-pull-up;
1817 qup_i2c5_default: qup-i2c5-default-state {
1820 drive-strength = <2>;
1821 bias-pull-up;
1824 qup_i2c6_default: qup-i2c6-default-state {
1827 drive-strength = <2>;
1828 bias-pull-up;
1831 qup_i2c7_default: qup-i2c7-default-state {
1834 drive-strength = <2>;
1835 bias-disable;
1838 qup_i2c8_default: qup-i2c8-default-state {
1841 drive-strength = <2>;
1842 bias-pull-up;
1845 qup_i2c9_default: qup-i2c9-default-state {
1848 drive-strength = <2>;
1849 bias-pull-up;
1852 qup_i2c10_default: qup-i2c10-default-state {
1855 drive-strength = <2>;
1856 bias-pull-up;
1859 qup_i2c11_default: qup-i2c11-default-state {
1862 drive-strength = <2>;
1863 bias-pull-up;
1866 qup_i2c12_default: qup-i2c12-default-state {
1869 drive-strength = <2>;
1870 bias-pull-up;
1873 qup_i2c13_default: qup-i2c13-default-state {
1876 drive-strength = <2>;
1877 bias-pull-up;
1880 qup_i2c14_default: qup-i2c14-default-state {
1883 drive-strength = <2>;
1884 bias-disable;
1887 qup_i2c15_default: qup-i2c15-default-state {
1890 drive-strength = <2>;
1891 bias-disable;
1894 qup_i2c16_default: qup-i2c16-default-state {
1897 drive-strength = <2>;
1898 bias-disable;
1901 qup_i2c17_default: qup-i2c17-default-state {
1904 drive-strength = <2>;
1905 bias-disable;
1908 qup_i2c19_default: qup-i2c19-default-state {
1911 drive-strength = <2>;
1912 bias-disable;
1917 compatible = "qcom,prng-ee";
1920 clock-names = "core";
1923 intc: interrupt-controller@17a00000 {
1924 compatible = "arm,gic-v3";
1925 #interrupt-cells = <3>;
1926 interrupt-controller;
1927 #redistributor-regions = <1>;
1928 redistributor-stride = <0 0x20000>;
1935 compatible = "arm,armv7-timer-mem";
1936 #address-cells = <1>;
1937 #size-cells = <1>;
1940 clock-frequency = <19200000>;
1943 frame-number = <0>;
1951 frame-number = <1>;
1958 frame-number = <2>;
1965 frame-number = <3>;
1972 frame-number = <4>;
1979 frame-number = <5>;
1986 frame-number = <6>;
1995 compatible = "qcom,rpmh-rsc";
1999 reg-names = "drv-0", "drv-1", "drv-2";
2003 qcom,tcs-offset = <0xd00>;
2004 qcom,drv-id = <2>;
2005 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2008 rpmhcc: clock-controller {
2009 compatible = "qcom,sm8350-rpmh-clk";
2010 #clock-cells = <1>;
2011 clock-names = "xo";
2015 rpmhpd: power-controller {
2016 compatible = "qcom,sm8350-rpmhpd";
2017 #power-domain-cells = <1>;
2018 operating-points-v2 = <&rpmhpd_opp_table>;
2020 rpmhpd_opp_table: opp-table {
2021 compatible = "operating-points-v2";
2024 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2028 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2032 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2036 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2040 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2044 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2048 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2052 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2056 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2065 apps_bcm_voter: bcm-voter {
2066 compatible = "qcom,bcm-voter";
2071 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
2075 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
2078 clock-names = "xo", "alternate";
2080 #freq-domain-cells = <1>;
2084 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
2085 "jedec,ufs-2.0";
2089 phy-names = "ufsphy";
2090 lanes-per-direction = <2>;
2091 #reset-cells = <1>;
2093 reset-names = "rst";
2095 power-domains = <&gcc UFS_PHY_GDSC>;
2099 clock-names =
2117 freq-table-hz =
2130 compatible = "qcom,sm8350-qmp-ufs-phy";
2132 #address-cells = <2>;
2133 #size-cells = <2>;
2135 clock-names = "ref",
2141 reset-names = "ufsphy";
2150 #phy-cells = <0>;
2155 compatible = "qcom,sm8350-slpi-pas";
2158 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2163 interrupt-names = "wdog", "fatal", "ready",
2164 "handover", "stop-ack";
2167 clock-names = "xo";
2169 power-domains = <&rpmhpd SM8350_LCX>,
2171 power-domain-names = "lcx", "lmx";
2173 memory-region = <&pil_slpi_mem>;
2175 qcom,qmp = <&aoss_qmp>;
2177 qcom,smem-states = <&smp2p_slpi_out 0>;
2178 qcom,smem-state-names = "stop";
2182 glink-edge {
2183 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2186 mboxes = <&ipcc IPCC_CLIENT_SLPI
2190 qcom,remote-pid = <3>;
2193 compatible = "qcom,fastrpc";
2194 qcom,glink-channels = "fastrpcglink-apps-dsp";
2196 qcom,non-secure-domain;
2197 #address-cells = <1>;
2198 #size-cells = <0>;
2200 compute-cb@1 {
2201 compatible = "qcom,fastrpc-compute-cb";
2206 compute-cb@2 {
2207 compatible = "qcom,fastrpc-compute-cb";
2212 compute-cb@3 {
2213 compatible = "qcom,fastrpc-compute-cb";
2216 /* note: shared-cb = <4> in downstream */
2223 compatible = "qcom,sm8350-cdsp-pas";
2226 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2231 interrupt-names = "wdog", "fatal", "ready",
2232 "handover", "stop-ack";
2235 clock-names = "xo";
2237 power-domains = <&rpmhpd SM8350_CX>,
2239 power-domain-names = "cx", "mxc";
2243 memory-region = <&pil_cdsp_mem>;
2245 qcom,qmp = <&aoss_qmp>;
2247 qcom,smem-states = <&smp2p_cdsp_out 0>;
2248 qcom,smem-state-names = "stop";
2252 glink-edge {
2253 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2256 mboxes = <&ipcc IPCC_CLIENT_CDSP
2260 qcom,remote-pid = <5>;
2263 compatible = "qcom,fastrpc";
2264 qcom,glink-channels = "fastrpcglink-apps-dsp";
2266 qcom,non-secure-domain;
2267 #address-cells = <1>;
2268 #size-cells = <0>;
2270 compute-cb@1 {
2271 compatible = "qcom,fastrpc-compute-cb";
2277 compute-cb@2 {
2278 compatible = "qcom,fastrpc-compute-cb";
2284 compute-cb@3 {
2285 compatible = "qcom,fastrpc-compute-cb";
2291 compute-cb@4 {
2292 compatible = "qcom,fastrpc-compute-cb";
2298 compute-cb@5 {
2299 compatible = "qcom,fastrpc-compute-cb";
2305 compute-cb@6 {
2306 compatible = "qcom,fastrpc-compute-cb";
2312 compute-cb@7 {
2313 compatible = "qcom,fastrpc-compute-cb";
2319 compute-cb@8 {
2320 compatible = "qcom,fastrpc-compute-cb";
2332 compatible = "qcom,sm8350-usb-hs-phy",
2333 "qcom,usb-snps-hs-7nm-phy";
2336 #phy-cells = <0>;
2339 clock-names = "ref";
2345 compatible = "qcom,sm8250-usb-hs-phy",
2346 "qcom,usb-snps-hs-7nm-phy";
2349 #phy-cells = <0>;
2352 clock-names = "ref";
2357 usb_1_qmpphy: phy-wrapper@88e9000 {
2358 compatible = "qcom,sm8350-qmp-usb3-phy";
2362 #address-cells = <2>;
2363 #size-cells = <2>;
2369 clock-names = "aux", "ref_clk_src", "com_aux";
2373 reset-names = "phy", "common";
2382 #phy-cells = <0>;
2383 #clock-cells = <0>;
2385 clock-names = "pipe0";
2386 clock-output-names = "usb3_phy_pipe_clk_src";
2390 usb_2_qmpphy: phy-wrapper@88eb000 {
2391 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2394 #address-cells = <2>;
2395 #size-cells = <2>;
2402 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2406 reset-names = "phy", "common";
2412 #phy-cells = <0>;
2413 #clock-cells = <0>;
2415 clock-names = "pipe0";
2416 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2421 compatible = "qcom,sm8350-dc-noc";
2423 #interconnect-cells = <1>;
2424 qcom,bcm-voters = <&apps_bcm_voter>;
2428 compatible = "qcom,sm8350-gem-noc";
2430 #interconnect-cells = <1>;
2431 qcom,bcm-voters = <&apps_bcm_voter>;
2434 system-cache-controller@9200000 {
2435 compatible = "qcom,sm8350-llcc";
2437 reg-names = "llcc_base", "llcc_broadcast_base";
2441 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2444 #address-cells = <2>;
2445 #size-cells = <2>;
2453 clock-names = "cfg_noc",
2459 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2461 assigned-clock-rates = <19200000>, <200000000>;
2463 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2467 interrupt-names = "hs_phy_irq",
2472 power-domains = <&gcc USB30_PRIM_GDSC>;
2484 phy-names = "usb2-phy", "usb3-phy";
2489 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2492 #address-cells = <2>;
2493 #size-cells = <2>;
2502 clock-names = "cfg_noc",
2509 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2511 assigned-clock-rates = <19200000>, <200000000>;
2513 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2517 interrupt-names = "hs_phy_irq",
2522 power-domains = <&gcc USB30_SEC_GDSC>;
2534 phy-names = "usb2-phy", "usb3-phy";
2538 dispcc: clock-controller@af00000 {
2539 compatible = "qcom,sm8350-dispcc";
2548 clock-names = "bi_tcxo",
2555 #clock-cells = <1>;
2556 #reset-cells = <1>;
2557 #power-domain-cells = <1>;
2559 power-domains = <&rpmhpd SM8350_MMCX>;
2560 power-domain-names = "mmcx";
2564 compatible = "qcom,sm8350-adsp-pas";
2567 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2572 interrupt-names = "wdog", "fatal", "ready",
2573 "handover", "stop-ack";
2576 clock-names = "xo";
2578 power-domains = <&rpmhpd SM8350_LCX>,
2580 power-domain-names = "lcx", "lmx";
2582 memory-region = <&pil_adsp_mem>;
2584 qcom,qmp = <&aoss_qmp>;
2586 qcom,smem-states = <&smp2p_adsp_out 0>;
2587 qcom,smem-state-names = "stop";
2591 glink-edge {
2592 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2595 mboxes = <&ipcc IPCC_CLIENT_LPASS
2599 qcom,remote-pid = <2>;
2602 compatible = "qcom,fastrpc";
2603 qcom,glink-channels = "fastrpcglink-apps-dsp";
2605 qcom,non-secure-domain;
2606 #address-cells = <1>;
2607 #size-cells = <0>;
2609 compute-cb@3 {
2610 compatible = "qcom,fastrpc-compute-cb";
2615 compute-cb@4 {
2616 compatible = "qcom,fastrpc-compute-cb";
2621 compute-cb@5 {
2622 compatible = "qcom,fastrpc-compute-cb";
2631 thermal_zones: thermal-zones {
2632 cpu0-thermal {
2633 polling-delay-passive = <250>;
2634 polling-delay = <1000>;
2636 thermal-sensors = <&tsens0 1>;
2639 cpu0_alert0: trip-point0 {
2645 cpu0_alert1: trip-point1 {
2658 cooling-maps {
2661 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2668 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2676 cpu1-thermal {
2677 polling-delay-passive = <250>;
2678 polling-delay = <1000>;
2680 thermal-sensors = <&tsens0 2>;
2683 cpu1_alert0: trip-point0 {
2689 cpu1_alert1: trip-point1 {
2702 cooling-maps {
2705 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2712 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2720 cpu2-thermal {
2721 polling-delay-passive = <250>;
2722 polling-delay = <1000>;
2724 thermal-sensors = <&tsens0 3>;
2727 cpu2_alert0: trip-point0 {
2733 cpu2_alert1: trip-point1 {
2746 cooling-maps {
2749 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2756 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2764 cpu3-thermal {
2765 polling-delay-passive = <250>;
2766 polling-delay = <1000>;
2768 thermal-sensors = <&tsens0 4>;
2771 cpu3_alert0: trip-point0 {
2777 cpu3_alert1: trip-point1 {
2790 cooling-maps {
2793 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2800 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2808 cpu4-top-thermal {
2809 polling-delay-passive = <250>;
2810 polling-delay = <1000>;
2812 thermal-sensors = <&tsens0 7>;
2815 cpu4_top_alert0: trip-point0 {
2821 cpu4_top_alert1: trip-point1 {
2834 cooling-maps {
2837 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2844 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2852 cpu5-top-thermal {
2853 polling-delay-passive = <250>;
2854 polling-delay = <1000>;
2856 thermal-sensors = <&tsens0 8>;
2859 cpu5_top_alert0: trip-point0 {
2865 cpu5_top_alert1: trip-point1 {
2878 cooling-maps {
2881 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2888 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2896 cpu6-top-thermal {
2897 polling-delay-passive = <250>;
2898 polling-delay = <1000>;
2900 thermal-sensors = <&tsens0 9>;
2903 cpu6_top_alert0: trip-point0 {
2909 cpu6_top_alert1: trip-point1 {
2922 cooling-maps {
2925 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2932 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2940 cpu7-top-thermal {
2941 polling-delay-passive = <250>;
2942 polling-delay = <1000>;
2944 thermal-sensors = <&tsens0 10>;
2947 cpu7_top_alert0: trip-point0 {
2953 cpu7_top_alert1: trip-point1 {
2966 cooling-maps {
2969 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2976 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2984 cpu4-bottom-thermal {
2985 polling-delay-passive = <250>;
2986 polling-delay = <1000>;
2988 thermal-sensors = <&tsens0 11>;
2991 cpu4_bottom_alert0: trip-point0 {
2997 cpu4_bottom_alert1: trip-point1 {
3010 cooling-maps {
3013 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3020 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3028 cpu5-bottom-thermal {
3029 polling-delay-passive = <250>;
3030 polling-delay = <1000>;
3032 thermal-sensors = <&tsens0 12>;
3035 cpu5_bottom_alert0: trip-point0 {
3041 cpu5_bottom_alert1: trip-point1 {
3054 cooling-maps {
3057 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3064 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3072 cpu6-bottom-thermal {
3073 polling-delay-passive = <250>;
3074 polling-delay = <1000>;
3076 thermal-sensors = <&tsens0 13>;
3079 cpu6_bottom_alert0: trip-point0 {
3085 cpu6_bottom_alert1: trip-point1 {
3098 cooling-maps {
3101 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3108 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3116 cpu7-bottom-thermal {
3117 polling-delay-passive = <250>;
3118 polling-delay = <1000>;
3120 thermal-sensors = <&tsens0 14>;
3123 cpu7_bottom_alert0: trip-point0 {
3129 cpu7_bottom_alert1: trip-point1 {
3142 cooling-maps {
3145 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3152 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3160 aoss0-thermal {
3161 polling-delay-passive = <250>;
3162 polling-delay = <1000>;
3164 thermal-sensors = <&tsens0 0>;
3167 aoss0_alert0: trip-point0 {
3175 cluster0-thermal {
3176 polling-delay-passive = <250>;
3177 polling-delay = <1000>;
3179 thermal-sensors = <&tsens0 5>;
3182 cluster0_alert0: trip-point0 {
3195 cluster1-thermal {
3196 polling-delay-passive = <250>;
3197 polling-delay = <1000>;
3199 thermal-sensors = <&tsens0 6>;
3202 cluster1_alert0: trip-point0 {
3215 aoss1-thermal {
3216 polling-delay-passive = <250>;
3217 polling-delay = <1000>;
3219 thermal-sensors = <&tsens1 0>;
3222 aoss1_alert0: trip-point0 {
3230 gpu-top-thermal {
3231 polling-delay-passive = <250>;
3232 polling-delay = <1000>;
3234 thermal-sensors = <&tsens1 1>;
3237 gpu1_alert0: trip-point0 {
3245 gpu-bottom-thermal {
3246 polling-delay-passive = <250>;
3247 polling-delay = <1000>;
3249 thermal-sensors = <&tsens1 2>;
3252 gpu2_alert0: trip-point0 {
3260 nspss1-thermal {
3261 polling-delay-passive = <250>;
3262 polling-delay = <1000>;
3264 thermal-sensors = <&tsens1 3>;
3267 nspss1_alert0: trip-point0 {
3275 nspss2-thermal {
3276 polling-delay-passive = <250>;
3277 polling-delay = <1000>;
3279 thermal-sensors = <&tsens1 4>;
3282 nspss2_alert0: trip-point0 {
3290 nspss3-thermal {
3291 polling-delay-passive = <250>;
3292 polling-delay = <1000>;
3294 thermal-sensors = <&tsens1 5>;
3297 nspss3_alert0: trip-point0 {
3305 video-thermal {
3306 polling-delay-passive = <250>;
3307 polling-delay = <1000>;
3309 thermal-sensors = <&tsens1 6>;
3312 video_alert0: trip-point0 {
3320 mem-thermal {
3321 polling-delay-passive = <250>;
3322 polling-delay = <1000>;
3324 thermal-sensors = <&tsens1 7>;
3327 mem_alert0: trip-point0 {
3335 modem1-top-thermal {
3336 polling-delay-passive = <250>;
3337 polling-delay = <1000>;
3339 thermal-sensors = <&tsens1 8>;
3342 modem1_alert0: trip-point0 {
3350 modem2-top-thermal {
3351 polling-delay-passive = <250>;
3352 polling-delay = <1000>;
3354 thermal-sensors = <&tsens1 9>;
3357 modem2_alert0: trip-point0 {
3365 modem3-top-thermal {
3366 polling-delay-passive = <250>;
3367 polling-delay = <1000>;
3369 thermal-sensors = <&tsens1 10>;
3372 modem3_alert0: trip-point0 {
3380 modem4-top-thermal {
3381 polling-delay-passive = <250>;
3382 polling-delay = <1000>;
3384 thermal-sensors = <&tsens1 11>;
3387 modem4_alert0: trip-point0 {
3395 camera-top-thermal {
3396 polling-delay-passive = <250>;
3397 polling-delay = <1000>;
3399 thermal-sensors = <&tsens1 12>;
3402 camera1_alert0: trip-point0 {
3410 cam-bottom-thermal {
3411 polling-delay-passive = <250>;
3412 polling-delay = <1000>;
3414 thermal-sensors = <&tsens1 13>;
3417 camera2_alert0: trip-point0 {
3427 compatible = "arm,armv8-timer";